$readmem warning : order incompatible

[kuldeep]

Evereytime i try to use readmemh in my verification environment i get
following warning..

$ncelab: *W,MEMODR <PATH of file> "$readmem default memory order
incompatible with IEEE1364."

any pointers will help..
thanx
Kuldeep

 

[Jim Wu]

It will be helpful if you can post a portion of your memory data file.

Jim Wu
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips

"kuldeep" <kkdeep@mailcity.com> wrote in message
news:a0f016a9.0309152127.e3d382a@posting.google.com...

Evereytime i try to use readmemh in my verification environment i get
following warning..

$ncelab: *W,MEMODR <PATH of file> "$readmem default memory order
incompatible with IEEE1364."

any pointers will help..
thanx
Kuldeep

 

[Eyck Jentzsch]

Hi,
trying 'nchelp ncelab MEMODR' gives the following:

ncelab/MEMODR =
When a default address range is used with the $readmem system
task, the memory is filled starting from the lowest address on
the memory definition, rather than the left address. This matches
the behavior of Verilog-XL. It does not match the Verilog-XL
documentation or the IEEE1364 standard. Early versions of
NC-Verilog matched the IEEE1364 standard, so this is a change
to the behavior. Dependency on this behavior can be avoided by
declaring the memory with the lowest address on the left, or by
specifying both the starting and ending address to $readmem.

HTH

-Eyck

 

[Steven Sharp]

kkdeep@mailcity.com (kuldeep) wrote in message news:<a0f016a9.0309152127.e3d382a@posting.google.com>...

Evereytime i try to use readmemh in my verification environment i get
following warning..

$ncelab: *W,MEMODR <PATH of file> "$readmem default memory order
incompatible with IEEE1364."

Someone else has already posted how to get extended help on warning
and error messages from the NC tools. That may provide you with
enough information. In case it doesn't:

You can ignore this warning as long as you aren't expecting $readmem
to behave the way that the IEEE 1364 standard says it does. You can
eliminate the warning message with "-nowarn MEMODR". You can eliminate
the cause of the warning by reversing your memory declaration indices
to make the leftmost bound be the smaller number instead of the larger
one (e.g. change "reg [7:0] m [1023:0];" to "reg [7:0] m [0:1023];").
For a memory declared that way, the IEEE standard specifies the same
order that simulators actually implement.

This warning will probably be eliminated from NC-Verilog before long.
The IEEE 1364 standard is finally being changed to match what all the
simulators actually do.

 

[kuldeep]

thanks a lot everybody..that solved the problem...


<SNIP>