reading the stimuls from input file

Hello

I want to use a text file to supply signals to the two input ports in
my program. the type of input ports is std_logic_vector(14 downto 0)

the content of the file is follow

QOUT=00000011011101 IOUT=00000101001110
QOUT=00000000000000 IOUT=00000000011000
QOUT=11111101101100 IOUT=00000101110100
QOUT=00000000000000 IOUT=00000000000000
QOUT=00000010010100 IOUT=00000101110100
QOUT=00000000000000 IOUT=00000000001110
QOUT=11111110111001 IOUT=00000110001001

QOUT is the first signal IOUT is the second

the problem that I don't now how to share this string into two
separate parts

how canI use the textio package functions to realize this problem?

Thanks

 

[Mike Treseler]

my24101974@yahoo.com wrote:

how canI use the textio package functions to realize this problem?

Consider declaring constant vector arrays in your testbench
with the same data.

Then you don't need textio and you get syntax checking for free.

-- Mike Treseler

 

[VhdlCohen]

I want to use a text file to supply signals to the two input ports in
my program. the type of input ports is std_logic_vector(14 downto 0)

the content of the file is follow

QOUT=00000011011101 IOUT=00000101001110
QOUT=00000000000000 IOUT=00000000011000
QOUT=11111101101100 IOUT=00000101110100
QOUT=00000000000000 IOUT=00000000000000
QOUT=00000010010100 IOUT=00000101110100
QOUT=00000000000000 IOUT=00000000001110
QOUT=11111110111001 IOUT=00000110001001

QOUT is the first signal IOUT is the second

the problem that I don't now how to share this string into two
separate parts

how canI use the textio package functions to realize this problem?

1. define a variable V_string5 of type string(1 to 4), and V_string6 (string(1
to6)
2. Following a readline into L, do a read with v to consume the 1st 5
characters (QOUT=)
Read(L, V_string5)
3. do a read of 1st vector into a length 14 (Vqout_std14)
READ(L, Vqout_std14)
4. Read(L, V_string6) to consume " IOUT="
5. do a read of 1st vector into a length 14 (Viout_std14)
READ(L, Viout_std14)
You may want to write a procedure that does all of that, and returns the 2
variables.

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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