Reading text files.

Guest
I am looking for the easiest way possible to read a text file into
SystemVerilog.

First, a little background:

I have six years of experience with VHDL, which I used to use to make
command-driven testbenches. I could write testbenches that looked
like this:

RESET 10
IDLE 12
WRITE ABCD1234 DEADBEEF
IDLE 6
READ 1234ABCD FEEDFEED

etc. etc. etc.

I would now like to do the same thing in Verilog and/or SystemVerilog,
but cannot find an easy way to read and parse a simple text file. So
far, the ONLY thing that I have found is: http://www.chris.spear.net/pli/fileio.htm
which uses PLI (which seems like a bit of a hack). I would prefer
something built-in to the language itself.

And, of course, if VHDL can do it, then Verilog must be at least as
good, right ;)

I have done pretty well at learning Verilog, so my next hurdle is to
learn SystemVerilog, get into assertions, formal verification, etc.
(nothing like a drink from the firehose)
 
kevin.harrelson@gmail.com wrote:
I am looking for the easiest way possible to read a text file into
SystemVerilog.

First, a little background:

I have six years of experience with VHDL, which I used to use to make
command-driven testbenches. I could write testbenches that looked
like this:

RESET 10
IDLE 12
WRITE ABCD1234 DEADBEEF
IDLE 6
READ 1234ABCD FEEDFEED

etc. etc. etc.

I would now like to do the same thing in Verilog and/or SystemVerilog,
but cannot find an easy way to read and parse a simple text file. So
far, the ONLY thing that I have found is: http://www.chris.spear.net/pli/fileio.htm
which uses PLI (which seems like a bit of a hack). I would prefer
something built-in to the language itself.

And, of course, if VHDL can do it, then Verilog must be at least as
good, right ;)

I have done pretty well at learning Verilog, so my next hurdle is to
learn SystemVerilog, get into assertions, formal verification, etc.
(nothing like a drink from the firehose)
Click to expand...
Sure, you can do that in Verilog testbenches. You shouldn't even need
SystemVerilog. Verilog-2005 supports a lot of C-style file i/o, such as
$fscanf, which you can use to parse files. I'm sure Modelsim supports
this (I think I've used this myself), although some simulators might
not. (Synthesizers surely won't.) But you might want to do what I
usually do and just declare functions or tasks for RESET, WRITE, etc.,
and call those with the arguments, like this:

initial
begin
RESET(10);
IDLE(15);
WRITE(1234, 5678);
..
end

If you wanted the "script" in a separate file you could still do that
and just `include it.
-Kevin
 
On Jul 18, 7:48 pm, kevin.harrel...@gmail.com wrote:
I would now like to do the same thing in Verilog and/or SystemVerilog,
but cannot find an easy way to read and parse a simple text file. So
far, the ONLY thing that I have found is:http://www.chris.spear.net/pli/fileio.htm
which uses PLI (which seems like a bit of a hack). I would prefer
something built-in to the language itself.
Click to expand...
Verilog-2001 added similar C-like file I/O system tasks and functions
built-in. Any tool that is remotely up-to-date should support them.
 
On Jul 19, 4:48 am, kevin.harrel...@gmail.com wrote:
I am looking for the easiest way possible to read a text file into
SystemVerilog.

First, a little background:

I have six years of experience with VHDL, which I used to use to make
command-driven testbenches. I could write testbenches that looked
like this:

RESET 10
IDLE 12
WRITE ABCD1234 DEADBEEF
IDLE 6
READ 1234ABCD FEEDFEED

etc. etc. etc.

I would now like to do the same thing in Verilog and/or SystemVerilog,
but cannot find an easy way to read and parse a simple text file. So
far, the ONLY thing that I have found is:http://www.chris.spear.net/pli/fileio.htm
which uses PLI (which seems like a bit of a hack). I would prefer
something built-in to the language itself.

And, of course, if VHDL can do it, then Verilog must be at least as
good, right ;)

I have done pretty well at learning Verilog, so my next hurdle is to
learn SystemVerilog, get into assertions, formal verification, etc.
(nothing like a drink from the firehose)
Click to expand...
As other posters noted, it is equally easier/tougher to do it in
Verilog-2001 without the PLI. Since SystemVerilog is superset of V2K,
same applies. However this would mean your "test generation" is done
outside the testbench and you are not fully exploiting the power of
SystemVerilog. It is understandable if you have lot of legacy command
files of this type that you would like to reuse. Even in that case
there are additional benefits of SV - such as functional coverage etc.
In our SNUG 2007 India paper/poster we showed how to reuse a file
based setup in a SystemVerilog-VMM based environment thereby
leveraging on the legacy tests and moving new tests to constrained
random testing. Look for it in snug-universal.org if interested.

Good Luck
Ajeetha, CVC
www.noveldv.com
 
Hi Kevin,

I have some open source Systemverilog examples that might be useful
( trusster <> com ). The files to look at are teal_dictionary.sv and
teal_dirctionary.svh. They read a file and create a name, value
dictionary pair. Not exactly what you need, but the file IO muck is
there.

Fell free to contact me privately if you have any questions.

Take Care,
Mike <> trusster.com
 
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