reading synchronous RAM asynchronously?

hi

For synchronous RAM (for example, BRAM in xilinx) and signal a,b,c

MEM: RAMB16_S16
port map (we=>write_enable, rw =>read_write,.........)


I am curious if there is a way doing

a = MEM(0) -- assignment of value in address 0 to signal a
b = MEM(0) -- assignment of value in address 0 to signal b
c = MEM(0) -- assignment of value in address 0 to signal c
.... like this, so that memory values quickly assigned to signal ...

Or should always we use control signals (for example, write_enable,
read_write)?

 

[Andy Peters]

JEmoderatz@yahoo.com wrote:

hi

For synchronous RAM (for example, BRAM in xilinx) and signal a,b,c

MEM: RAMB16_S16
port map (we=>write_enable, rw =>read_write,.........)


I am curious if there is a way doing

a = MEM(0) -- assignment of value in address 0 to signal a
b = MEM(0) -- assignment of value in address 0 to signal b
c = MEM(0) -- assignment of value in address 0 to signal c
... like this, so that memory values quickly assigned to signal ...

Or should always we use control signals (for example, write_enable,
read_write)?

A synchronous RAM looks at the state of the control signals and the
address at the rising edge of the clock, so if you permanently enabled
writing, you'd always store whatever's on the data bus into the
location pointed to by the address bus on each clock edge.

Of course, a write-only memory isn't terribly useful, so I assume
you're implementing a dual-port RAM, right?

=-a