Reading internal signals through a testbench (PLI ???).

Hi all,
Through a testbench (Verilog ), how do I read the values of signals of
a sub module through a top module? This is required to match and assert
if the program is working correctly. If I am planning to use "Verilog
PLI" then in that case what access routines are available to monitor
internal signals of sub modules. Thank you for help.

Best Regards,

 

[Ajeetha]

Hi,
In verilog you have this "dot-operator" to do this, no need of PLI
for this. In your TB, do:

initial
begin
$display ("Internal signal value is %b",
top.dut.block_1.sig_name");

HTH
Ajeetha
www.noveldv.com

 

hi,
thanks for the reply. With the dot operator we can see the ports of
the internal signals. But is it true for signals also? Also please let
me know if Verilog PLI contains some routines to access internal
signals. Thanks.

Best Regards,

 

[Ajeetha]

For both the answer is YES, consult a Verilog book and a PLI book/LRM
for exact details.
Ajeetha
www.noveldv.com

 

Hi,
Is it possible to use verilog PLI for writing testbenches for the
design modules that are done in VHDL? Ex. I have a design fully in
VHDL, now in modelsim i can do mixed simulation like i can write
verilog testbench for this and simulate. Wether the same applies to PLI
also? Thanks.

 

[Ajeetha]

Modelsim can do mixed HDL sim. However accessing lower level signals in
VHDL is not allowed by VHDL. Look for Signal Spy in your Modelsim
manual for a Work around.

On PLI - what exactly is your Q? I don't follow you. PLI is an
interface to Verilog, for VHDL there is some thing called VHPI - yet to
standardize, lot of tools already support it though (VCSMX, NC, Aldec -
no MTI though).

HTH
Ajeetha
www.noveldv.com

 

Hi,
What I wanted to ask was that, we know we can simulate a VHDL design
with a verilog testbench. So suppose I have a design in VHDL and i
write verilog testbench for it then wether in this case PLI can be used
as PLI will be interfacing to verilog testbench only?
I tried this out but for access routines it fails when I define a
handle to a module. It gives some error. Maybe because in the main
design it the "entity" that is defined and not a "module". Please
correct me.

Best Regards,