A
Andreas Ehliar
Guest
A colleague just asked me a SystemVerilog question which I was unable
to answer. Perhaps some SystemVerilog language lawyer on this group
could answer the following question?
Basically: If you define a signal as an output port in an interface by
using a modport, what is supposed to happen if you read from this
signal? Especially if you never write to this signal in the module
itself. Personally I would guess this should be an error, but this
doesn't seem to be the case in practice:
* In ModelSim (6.4a), it seems like you can read this value just as if
it was declared as an input.
* In Precision (2008a.17) it seems to be synthesized as if noone is
driving the signal at all
(Below is a simple design which shows what I mean if my description above
is not clear. Sorry about the extremely descriptive identifier names
)
interface wishbone;
logic stb; // strobe
logic ack; // normal termination
modport master(
output stb,
input ack);
modport slave(
input stb,
output ack);
modport monitor(
output stb,ack);
endinterface: wishbone
module apa(input logic clk,rst,
output reg nisse);
wishbone w();
grmbl a(w);
grmbl2 b(w,nisse);
grmbl_master c(clk,rst,w);
endmodule
module grmbl(wishbone.slave w);
assign w.ack = w.stb;
endmodule
module grmbl2(wishbone.monitor w,output logic a);
assign a = w.ack; // <-- This part reads from an output!
// What is supposed to happen?
endmodule
module grmbl_master(input logic clk,rst,wishbone.master m);
logic toggle;
always_ff @(posedge clk) begin
if(rst) begin
toggle <= 1'b0;
end else begin
toggle <= !toggle;
end
end
assign m.stb = toggle;
endmodule
//Andreas
to answer. Perhaps some SystemVerilog language lawyer on this group
could answer the following question?
Basically: If you define a signal as an output port in an interface by
using a modport, what is supposed to happen if you read from this
signal? Especially if you never write to this signal in the module
itself. Personally I would guess this should be an error, but this
doesn't seem to be the case in practice:
* In ModelSim (6.4a), it seems like you can read this value just as if
it was declared as an input.
* In Precision (2008a.17) it seems to be synthesized as if noone is
driving the signal at all
(Below is a simple design which shows what I mean if my description above
is not clear. Sorry about the extremely descriptive identifier names
)interface wishbone;
logic stb; // strobe
logic ack; // normal termination
modport master(
output stb,
input ack);
modport slave(
input stb,
output ack);
modport monitor(
output stb,ack);
endinterface: wishbone
module apa(input logic clk,rst,
output reg nisse);
wishbone w();
grmbl a(w);
grmbl2 b(w,nisse);
grmbl_master c(clk,rst,w);
endmodule
module grmbl(wishbone.slave w);
assign w.ack = w.stb;
endmodule
module grmbl2(wishbone.monitor w,output logic a);
assign a = w.ack; // <-- This part reads from an output!
// What is supposed to happen?
endmodule
module grmbl_master(input logic clk,rst,wishbone.master m);
logic toggle;
always_ff @(posedge clk) begin
if(rst) begin
toggle <= 1'b0;
end else begin
toggle <= !toggle;
end
end
assign m.stb = toggle;
endmodule
//Andreas