Reading data into veriloga testbench from file

Hi,
I cannot find any routines in the verilog-A manual that describes how
to read data from a file.
I want to write a testbench that read textual data from a file
containing my stimuli in csv format and have this read by the
verilog-A testbench.

Maybe this feature hasn't been implemented? Could it be done with PLI
or a Tcl interface?

--
Svenn

 

[Andrew Beckett]

You can do it in AMS Designer because of Verilog functions ($fread, I think),
but not (yet) in spectre. It's coming sometime soon though.

The only function you have is the $table_model() function - which allows
interpolation.

PLI or Tcl won't help with Spectre - but could be used with AMS Designer (where
you don't need to use it since it is possible anyway!).

SpectreHDL has support for file reading (but SpectreHDL is not supported
in AMS Designer).

From a quick search, I think spectre is due to support a Verilog-A $fread in
IC5033 USR3 (due beginning of September).

Andrew.


On 10 Aug 2004 03:58:41 -0700, svenn.are@bjerkem.de wrote:

Hi,
I cannot find any routines in the verilog-A manual that describes how
to read data from a file.
I want to write a testbench that read textual data from a file
containing my stimuli in csv format and have this read by the
verilog-A testbench.

Maybe this feature hasn't been implemented? Could it be done with PLI
or a Tcl interface?

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd