Reading a real value into a module..

[kb33]

Hi,

I am interested in knowing how I can read in as an input a real value
into a verilog module.

Thanks,
kb33

 

[mk]

On 24 Mar 2006 09:01:33 -0800, "kb33" <kanchan.devarakonda@gmail.com>
wrote:

Hi,

I am interested in knowing how I can read in as an input a real value
into a verilog module.

Try $fscanf

 

Actually, I was interested in knowing if the "input" keyword could be
used to read in a real value. If I use $fscanf, the code wouldn't be
synthesizable, right?

kb33

 

[Ajeetha]

Hi,
Verilog does not allow real data type in input/output. You can pass
it as 64 bit vector and use $bitstoreal, $realtobits. But for
synthesis, most of the synthesis tools don't support real, so you will
need to define your own floating point unit kind of stuff.

HTH
Ajeetha, CVC
www.noveldv.com