"read/write synchronization is not available for the selecte

[lomtik]

Hi,
While synthesizing the code on Spartan 2 for free filter IP I've found
on internet, I am getting the following message.
The filter stores coefficients in rom entity, and intermediate results
in sram. The first one has only read option, while the last one
read/write.

Xilinx Webhelp does not have an article on that error message. It looks
like I have to use another device, but why wouldn't it support such a
simple structure? I doubd that though. Maybe I can modify the code
somehow.

Thank you very much



Synthesizing Unit <sram>.
Related source file is
D:/Xilinxworkdir/PSK_MOD_jan/LPF_16_100k_200k.vhdl.
INFO:Xst:1435 - HDL ADVISOR - Unable to extract a block RAM for signal
<RAMDATA>. The read/write synchronization appears to be READ_FIRST and
is not available for the selected family. A distributed RAM will
usually be created instead. To take advantage of block RAM resources,
you may want to revisit your RAM synchronization or check available
device families.
Found 512x10-bit single-port distributed RAM for signal <RAMDATA>.

..
...
....

Synthesizing Unit <rom>.
Related source file is
D:/Xilinxworkdir/PSK_MOD_jan/LPF_16_100k_200k.vhdl.
WARNING:Xst:653 - Signal <ROMDATA<0>> is used but never assigned. Tied
to value 0000000000000000.
WARNING:Xst:1781 - Signal <ROMDATA<401:511>> is used but never
assigned. Tied to default value.
INFO:Xst:1435 - HDL ADVISOR - Unable to extract a block RAM for signal
<ROMDATA>. The read/write synchronization appears to be READ_FIRST and
is not available for the selected family. A distributed RAM will
usually be created instead. To take advantage of block RAM resources,
you may want to revisit your RAM synchronization or check available
device families.
Found 16-bit register for signal <DOUT>.
Found 16-bit 512-to-1 multiplexer for signal <$n0002> created at
line 468.
Summary:
inferred 16 D-type flip-flop(s).
inferred 16 Multiplexer(s).
Unit <rom> synthesized.

 

[lomtik]

Here is ROM entity
Please note that sram entity has not only read, but also write process
statement.



entity rom is
Port (
CK : In std_logic;
RDN : In std_logic;
CSN : In std_logic;
ADDR : In std_logic_vector(8 downto 0);
DOUT : Out std_logic_vector(15 downto 0) );
end rom;

architecture STRUCTURE of rom is

subtype ROMWORD is std_logic_vector(15 downto 0);
type ROMARRAY is array (0 to 2**9 - 1) of ROMWORD;

signal ROMDATA : ROMARRAY;
signal ADDR_IN : integer range 0 to 2**9 - 1;
-- signal DIN_CHANGE, WRN_RISE : time := 0 ps;
signal addr_tmp : unsigned(8 downto 0);

begin -- architecture rom

----------------------------------------------------
gen_addr_tmp : process( ADDR )
begin -- process gen_addr_tmp

for i in 8 downto 0 loop
addr_tmp(i) <= ADDR(i);
end loop;

end process gen_addr_tmp;

----------------------------------------------------
ADDR_IN <= conv_integer(addr_tmp);

ROMDATA( 1) <= "0000000010010011";
ROMDATA( 2) <= "1111111001110100";
ROMDATA( 3) <= "1111110010110011";
ROMDATA( 4) <= "1111110100100010";
ROMDATA( 5) <= "0000001011000000";
ROMDATA( 6) <= "0000110111110100";
ROMDATA( 7) <= "0001101100010110";
ROMDATA( 8) <= "0010010000000011";
ROMDATA( 9) <= "0010010000000011";
ROMDATA( 10) <= "0001101100010110";
ROMDATA( 11) <= "0000110111110100";
ROMDATA( 12) <= "0000001011000000";
ROMDATA( 13) <= "1111110100100010";
ROMDATA( 14) <= "1111110010110011";
ROMDATA( 15) <= "1111111001110100";
ROMDATA( 16) <= "0000000010010011";
ROMDATA( 17) <= "0000000000000000";
-- ... all zeros assignments
ROMDATA(400) <= "0000000000000000";

--------------------------------------------------------------
rd_data : process(CK) -- modified Jan/25/2003
begin -- process rd_data

if(CK'event and CK = '1') then
if(RDN = '0' and CSN = '0') then
DOUT <= ROMDATA(ADDR_IN);
else
DOUT <= (others => '0');
end if;
end if;
end process rd_data;

--------------------------------------------------------------
end; -- architecture rom