Read/Write data from/to SRAM

[Oscar Garnica]

Hi,

We have tried to read/write data from/to SRAM (AS7C4096) using a tri-state
buffer to drive data bus but we are not being able to manage this task.
Whenever we try to read data from the memory we obtain the value 0x0000
although the memory word has been loaded with a different pattern.
Similarly, when we write data the final value in the memory word is 0x0000
regardless of the value we drive into the data bus.

Has anybody any idea about this? What are we doing wrong?

Thanks a lot

O. Garnica
UCM

 

[ALuPin]

"Oscar Garnica" <ogarnica@dacya.ucm.es> wrote in message news:<c8vtvf$6$1@thule.sim.ucm.es>...

Hi,

We have tried to read/write data from/to SRAM (AS7C4096) using a tri-state
buffer to drive data bus but we are not being able to manage this task.
Whenever we try to read data from the memory we obtain the value 0x0000
although the memory word has been loaded with a different pattern.
Similarly, when we write data the final value in the memory word is 0x0000
regardless of the value we drive into the data bus.

Has anybody any idea about this? What are we doing wrong?

Thanks a lot

O. Garnica
UCM

Have a closer look at the control signals OE_N, WE_N, CS_N.
Is the sram address stable before these signals are asserted for write cycle?

Rgds

 

[Tommy Thorn]

ALuPin wrote:

"Oscar Garnica" <ogarnica@dacya.ucm.es> wrote in message news:<c8vtvf$6$1@thule.sim.ucm.es>...

We have tried to read/write data from/to SRAM (AS7C4096) using a tri-state
buffer to drive data bus but we are not being able to manage this task.
Whenever we try to read data from the memory we obtain the value 0x0000
although the memory word has been loaded with a different pattern.
Similarly, when we write data the final value in the memory word is 0x0000
regardless of the value we drive into the data bus.

Has anybody any idea about this? What are we doing wrong?


Have a closer look at the control signals OE_N, WE_N, CS_N.
Is the sram address stable before these signals are asserted for write cycle?

Oscar, with that level of detail (= lack thereof) we can't help much.

In my SRAM controller (Cyclone hooked up to two IDT71V416) I take four
(10ns) cycles for write:
- one to turn of the output enable (OE_N = 0),
- one to load the address and data, and open the output drivers,
- one to write the data (WE_N = 1)
- one to turn it back off (WE_N = 0)

For writes after write in a row, the first cycle can be shaved off, but
I haven't been able to bring the write process down under three cycles
in spite of the datasheet's claimed 0 tWR. I don't know if that's
normal (this is with the Nios development board, Cyclone edition).

I'm more concerned about the maximum read performance. Reading the data
sheet, the positive (4 ns) tOH made me think that I could sustain a read
every cycle (the tRC is 10ns as is my cycle time), but my testing has
given inconsistent results.

Question to the experts: Is this (simplified example) safe?

assign fse_a = read_addr;
always @(posedge clk) begin
read_data <= fse_d; // SRAM data
read_addr <= read_addr + 4;
end

(Obviously the read_data would correspond to the previous cycle read_addr).

Thanks,
Tommy