Read from File on two clock events

[Ashu]

Hi,

I have written a Test bench to read test vectors from a file to test
UART.

The test vector file includes control register and test data in it.

I order to write to Control registers of UART i need to fire Test
vectors on Global clock event.

But when I need to fire test vectors to my RX pin they should be
sampled at baud clock rate.

Though I have implemented a simple mechanism which indirectly reads the
file at two different rates.

Can anyone help me out with more efficient way.
(Note:I am using single test vector file)

If required I can post my Code.



Thanks
Ashish

 

[Ashu]

Here is code.

Please comment.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;

ENTITY UART_TB1_vhd IS
END UART_TB1_vhd;

ARCHITECTURE behavior OF UART_TB1_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UART
PORT(
add : IN std_logic_vector(1 downto 0);
rd : IN std_logic;
wr : IN std_logic;
gclk : IN std_logic;
reset : IN std_logic;
rx : IN std_logic;
data : INOUT std_logic_vector(7 downto 0);
frame_error : OUT std_logic;
tx : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL rd : std_logic := '0';
SIGNAL wr : std_logic := '0';
SIGNAL gclk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL rx : std_logic := '0';
SIGNAL add : std_logic_vector(1 downto 0) := (others=>'0');

--BiDirs
SIGNAL data : std_logic_vector(7 downto 0);

--Outputs
SIGNAL frame_error : std_logic;
SIGNAL tx : std_logic;
signal simtime:time:=0 ns;
signal bclk:std_logic:='0';
signal gcount:integer:=0;
signal testcount:integer:=0;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: UART PORT MAP(
add => add,
data => data,
rd => rd,
wr => wr,
gclk => gclk,
reset => reset,
frame_error => frame_error,
tx => tx,
rx => rx
);

--*************************** File
IO**********************************************************************************
tb : PROCESS(testcount,gcount)
file infile:text is in "inputdat.txt";
file outfile:text is out "outputdat.txt";
variable myline:line;
variable testvector:std_logic_vector(15 downto 0):="0000000000000000";
alias test_reset:std_logic is testvector(15);
alias test_rd:std_logic is testvector(14);
alias test_wr:std_logic is testvector(13);
alias test_add:std_logic_vector(1 downto 0) is testvector(12 downto
11);
alias test_rx:std_logic is testvector(10);
alias test_data:std_logic_vector(7 downto 0) is testvector(7 downto
0);
-- variable ctr:integer range 0 to 1023:=0;

BEGIN

if not endfile (infile) then

if gcount<10 then

readline(infile,myline);
read(myline,testvector);
reset<=test_reset;
rd<=test_rd;
wr<=test_wr;
data<=test_data;
add<=test_add;
rx<=test_rx;
elsif testcount <200 then
readline(infile,myline);
read(myline,testvector);
reset<=test_reset;
rd<=test_rd;
wr<=test_wr;
data<=test_data;
add<=test_add;
rx<=test_rx;
end if;

end if;

END PROCESS;



--*************** Increase global counter to track the configuration of
UART
-- Use this count to read the initial test vectors for configuring the
UART
globalcountrocess(gclk)

begin

if gclk'event and gclk='1' then

if gcount<10 then

gcount<=gcount+1;

end if;
end if;
end process globalcount;

--******************************Test vector counter
tcountrocess(bclk)

begin

if bclk'event and bclk='1' then

if gcount=10 and testcount<200 then

testcount<=testcount+1;

end if;
end if;

end process tcount;



--****************************************END File
IO*********************************************************************

gclk<=not gclk after 10 ns;
bclk<=not bclk after 80 ns;
END;

 

[Mike Treseler]

Ashu wrote:

I have written a Test bench to read test vectors from a file to test
UART. Can anyone help me out with more efficient way.

Here's one example:
http://home.comcast.net/~mike_treseler/test_uart.vhd

-- Mike Treseler

 

[Ashu]

Thank you Mike.