Read a reg value from the outer module without declaring por

hi all....
Can i read a variable in the inner module from the outer module?.
without declare it as a out port.
regards
subin

 

[Jeremy Ralph]

Unfortunately, to the best of my knowledge, VHDL doesn't allow you to
sniff signals that are buried within a hierarchy, like Verilog does.
Your simulator should allow you to probe and force such values though.

VHDL does however allow global signals which can be useful for
verification purposes. To create a global signal create a package with
a signal definition in it. Then you will have access to the signal
from wherever you include the package.

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps

 

[Jeremy Ralph]

Ooops... this is the comp.lang.verilog not comp.lang.vhdl as my
previous message assumed.

Verilog does allow you to access internals using 'hierarchical
referencing'. For example:

always @(topmodule.innermodule.regname)
$display("reg value is %0d", topmodule.innermodule.regname);

 

Thanks Jeremy Ralph...