Randomization in system verilog

[Melvin]

Hi,

I wanted to try randomization using System Verilog.

I did the following:

class rand_class_ins
rand bit direction;
endclass

rand_class_ins rand_class
rand_class = new;

task some_super_class
rand_class.randomize();
$display("%d",direction");
endtask

However the above task irrespective of how much ever times I call it
returns direction as the same value.
I also checked if randomization is taking place properly by
rand_class.randomize() function which is returning one.


Thanks
Verilog baby

 

[Jonathan Bromley]

On May 19, 2:21 pm, Melvin wrote:

class rand_class_ins
rand bit direction;
endclass

rand_class_ins rand_class
rand_class = new;

task some_super_class
rand_class.randomize();
$display("%d",direction");
endtask

However the above task irrespective of how much ever times I call it
returns direction as the same value.

I got rid of your various syntax errors:

module foo;
class rand_class_ins;
rand bit direction;
endclass
rand_class_ins rand_class = new;
task some_class;
rand_class.randomize();
$display("dir=%d", rand_class.direction);
endtask
initial
repeat (10)
some_class();
endmodule

and this is the result I saw:

dir=1
dir=0
dir=1
dir=1
dir=1
dir=1
dir=1
dir=1
dir=1
dir=0

Can you show us the code you really used, instead of
some random nonsense? I wonder if perhaps there was
another variable "direction" in your top level module,
and you're seeing the unchanging value of that variable
because you're not looking inside the object?
--
Jonathan Bromley