Random Number Generator??

K

Kingsley Oteng

Guest
Does VHDL have a random number generator built in it? Something like the RND
command in C++?? I have a system whose performance I would like to test by
getting it to randomly generate inputs...problem is I don't know how to
randomly generate numbers....

- Kingsley
 
Kingsley Oteng <k.oteng@student.unsw.edu.au> wrote:
Does VHDL have a random number generator built in it? Something like the RND
command in C++?? I have a system whose performance I would like to test by
getting it to randomly generate inputs...problem is I don't know how to
randomly generate numbers....

- Kingsley


How about a chain of FF with mod2 adders?
Click to expand...
--
Wing Wong.
wing.fong.wong@thisicrap.ieee.isaloadofbs.org
 
Have a look at

http://verificationguild.com/modules.php?name=Downloads&d_op=viewdownload&cid=3

Ronald

Kingsley Oteng wrote:
Does VHDL have a random number generator built in it? Something like the RND
command in C++?? I have a system whose performance I would like to test by
getting it to randomly generate inputs...problem is I don't know how to
randomly generate numbers....

- Kingsley
Click to expand...
 
On Wed, 28 Apr 2004 08:34:14 +1000, "Kingsley Oteng"
<k.oteng@student.unsw.edu.au> wrote:

Does VHDL have a random number generator built in it? Something like the RND
command in C++?? I have a system whose performance I would like to test by
getting it to randomly generate inputs...problem is I don't know how to
randomly generate numbers....
Click to expand...
VHDL has an excellent built-in random number generator, if you count
the IEEE.math_real package as "built-in". It's called UNIFORM.
You need to keep two seed values (of type POSITIVE) on its behalf.
Every time you invoke it, it updates your seed values and gives you
a random REAL value in the range 0 to (not quite) 1.0. You can
then massage this REAL value any way you want to get your random
bit pattern or whatever.

library ieee;
use ieee.math_real.all; -- for UNIFORM, TRUNC
use ieee.numeric_std.all; -- for TO_UNSIGNED
....

process
-- Seed values for random generator
variable seed1, seed2: positive;
-- Random real-number value in range 0 to 1.0
variable rand: real;
-- Random integer value in range 0..4095
variable int_rand: integer;
-- Random 12-bit stimulus
variable stim: std_logic_vector(11 downto 0);
begin
-- initialise seed1, seed2 if you want -
-- otherwise they're initialised to 1 by default
loop -- testbench stimulus loop?
UNIFORM(seed1, seed2, rand);
-- get a 12-bit random value...
-- 1. rescale to 0..(nearly)4096, find integer part
int_rand := INTEGER(TRUNC(rand*4096.0));
-- 2. convert to std_logic_vector
stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
...

Modify according to taste.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Jonathan Bromley a écrit:

VHDL has an excellent built-in random number generator, if you count
the IEEE.math_real package as "built-in". It's called UNIFORM.
You need to keep two seed values (of type POSITIVE) on its behalf.
Every time you invoke it, it updates your seed values and gives you
a random REAL value in the range 0 to (not quite) 1.0. You can
then massage this REAL value any way you want to get your random
bit pattern or whatever.
Click to expand...
Great!
I was just about to ask some help about the uniform procedure (I came up
with a nice random jitter generator last week but my use of uniform is a
bit uncertain). Your post answers everything I wanted to ask, thanks a
lot :eek:)

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
 
Thanks for the informations, but does anyone know how to get the
IEEE.math_real library...?

Thanks again..
 
Does anyone know where can I get the IEEE.math_real library?

Looking forward to hear from you,

AbouHimed
 
On Fri, 21 May 2004 00:11:56 -0400, "AbouHimed"
<laylakazem@hotmail.com> wrote:

Thanks for the informations, but does anyone know how to get the
IEEE.math_real library...?
Click to expand...
It's distributed with your simulator, unless you have a truly
bizarre simulator.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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