Random logic verilog gate netlist generator

[Simon S. IBM]

We have a need to create hundreds of non proprietary digital test structures,
each which would fit a pre-determined pinouts for a pre-determined
block size & a pre-determined block shape (e.g., rectilinear).

Can you provide a pointer to a good random logic verilog gate netlist generator?

I'd expect to feed it technology & macro LEF; the input & output
pins; and either a gate count, or a block area (most likely a gate count).

After running this random-logic verilog-gate generator, we would
then place & route the results. The easy part is the place & route.
The hard part is to come up with hundreds of non-proprietary
sets of random (well mixed) gates to fill the blocks up with.

Any pointers would be appreciated.
Simon

 

[Glenn Heraty]

cmos_nand_gate@yahoo.com (Simon S. IBM) wrote in message news:<3520d403.0402131953.7b664fee@posting.google.com>...

Can you provide a pointer to a good random logic verilog
gate netlist generator?

Such a tool does not exist. It will never exist.
I tried to write one long ago but I failed.

What you'll need to do is find some generic RTL
and just place and route that generic RTL.

I use ARM or Sparc code which is out there in
the public domain.

Just snatch a few tens of thousands of lines
and place and route it. Send me an email and
I'll send you the complete ARM core or Sparc.

Glenn

 

[Kelvin L.]

ghjrtyweq@yahoo.com (Glenn Heraty) wrote in message news:<5278e2c8.0402152122.3480b3cb@posting.google.com>...

cmos_nand_gate@yahoo.com (Simon S. IBM) wrote in message news:<3520d403.0402131953.7b664fee@posting.google.com>...
Can you provide a pointer to a good random logic verilog
gate netlist generator?

Such a tool does not exist.

Pardon me, but, you're absolutely wrong!
I have seen a handful of these tools (often used for p&r tests).

In fact, I have a perl program (gateGen.pl) and a C program
(genGates.c) which I'll send to you (as soon as I dig them out
of my src directory).

They work wonders.

I even seem to remember a skill program (generateVerilog.il ???)
posted to comp.lang.verilog or comp.cad.cadence a few years back
(someone refresh my failing memory).

The perl program was provided to me by an application engineer
at Cadence who used it to generate test fixtures. It could use
some work, for example, it asks you the number of pins but then
splits that number in half to make half input and half output
pins of names it chooses. This necessitates manual editing of
the resultant verilog gate netlist to get the pins correct, but,
that's generally an easy task. It does generate as many gates as
you tell it, in random arrangement, all hooked up properly.

The C program works fine but I hate compiling (I never was that
good at it), so I use the perl program almost exclusively with
a bit of vi editing of the results. I use the Cadence verilogin
feature to generate, place, and route a schematic so that the
nearly instantaneous DFII schematic and layout results are Assura
DRC/LVS correct. I often use the Cadence design kit at 180nm
(I hear they have a new kit at 90 and another at 65nm) which
contains plenty of standard cells, LEF, TLF, CDL, EDIF symbols,
Pcells, DRC/LVS/RCX rules, etc. for my purposes.

Let the group know how my two programs work for you.
tenlayermatal

 

[B. Joshua Rosen]

On Fri, 13 Feb 2004 19:53:32 -0800, Simon S. IBM wrote:

We have a need to create hundreds of non proprietary digital test structures,
each which would fit a pre-determined pinouts for a pre-determined
block size & a pre-determined block shape (e.g., rectilinear).

Can you provide a pointer to a good random logic verilog gate netlist generator?

I'd expect to feed it technology & macro LEF; the input & output
pins; and either a gate count, or a block area (most likely a gate count).

After running this random-logic verilog-gate generator, we would
then place & route the results. The easy part is the place & route.
The hard part is to come up with hundreds of non-proprietary
sets of random (well mixed) gates to fill the blocks up with.

Any pointers would be appreciated.
Simon

Try HDLmaker

http://www.polybus.com/hdlmaker/users_guide/

HDLmaker has a C like language that will allow you to generate this sort
of thing. Also HDLmaker can generate Xilinx floorplanning statements.

BTW It looks like you are looking for Xilinx FPGA test patterns. I have an
extensible set of Xilinx FPGA test patterns that I offer as a product.

http://www.polybus.com/xilinx_test_patterns/

 

[Jahagirdar Vijayvithal S]

* Glenn Heraty <ghjrtyweq@yahoo.com>:

cmos_nand_gate@yahoo.com (Simon S. IBM) wrote in message news:<3520d403.0402131953.7b664fee@posting.google.com>...
Can you provide a pointer to a good random logic verilog
gate netlist generator?

Such a tool does not exist. It will never exist.
I tried to write one long ago but I failed.

I had written a tool for a similar purpose(congestion analysis

of different bus structures) using a different set of inputs (I was
interested in module level behaviour and had the freedom to generate my
own modules with random IOs names).
It should be possible to create a simple tool for your purpose.
One possible approach using the verilog model of the gates would be to
1> Read in all the files_names in an array.
2> Randomly pick up 'required_number_of_gates' elements from the array
3> Create a suitable command string for one of the freely available
verilog structural integration tool (I would have recommended 'make_top'
available at tclforeda.net because it simplifies #5 but looks like that
domain name is now pointing at some other place. Anyone knows what
happened to it?)
4> Run the tool to generate the required template.
5> Get all the input ports of the modules and randomly connect them
to
a> tie0/tie1
b> Primary Input
c> One of the output port of another module.
6> Connect some of the randomly selected output ports to 'Primary output'

You can constrain #5 and #6 for clock/reset/system bus/PI/PO/gates to
have a more realistic behavior

Based on my experience, with a good scripting language(Perl?) you can
have the tool up and running in less than a day.

Regards
Jahagirdar Vijayvithal S

 

[Pooja Maheshwari]

You can try Ccric/Cgen tool from following link

"http://www.eecg.toronto.edu/~jayar/software/Cgen/Cgen.html"

It generates random design in VHDL format then you can use
some translation program to covert it to Verilog.

- Pooja

"Simon S. IBM" wrote:

We have a need to create hundreds of non proprietary digital test structures,
each which would fit a pre-determined pinouts for a pre-determined
block size & a pre-determined block shape (e.g., rectilinear).

Can you provide a pointer to a good random logic verilog gate netlist generator?

I'd expect to feed it technology & macro LEF; the input & output
pins; and either a gate count, or a block area (most likely a gate count).

After running this random-logic verilog-gate generator, we would
then place & route the results. The easy part is the place & route.
The hard part is to come up with hundreds of non-proprietary
sets of random (well mixed) gates to fill the blocks up with.

Any pointers would be appreciated.
Simon

 

[Ramesh]

Gnl is another tool with similar generator functionality.

http://www.elis.ugent.be/~pvrplaet/gnl/

It doesn't take much work to convert the netlist writer in gnl to a
verilog writer. (Same applies to Cgen).

Gnl doesn't have the characterization (circ) feature of Ccirc/Cgen. If
you are looking at generation from templates you write both tools are
interesting.

Pooja Maheshwari <mpooja@agere.com> wrote in message news:<4032072D.40064D56@agere.com>...

You can try Ccric/Cgen tool from following link

"http://www.eecg.toronto.edu/~jayar/software/Cgen/Cgen.html"

It generates random design in VHDL format then you can use
some translation program to covert it to Verilog.

- Pooja

"Simon S. IBM" wrote:

We have a need to create hundreds of non proprietary digital test structures,
each which would fit a pre-determined pinouts for a pre-determined
block size & a pre-determined block shape (e.g., rectilinear).

Can you provide a pointer to a good random logic verilog gate netlist generator?

....