Ramp in verilog....how?

[Dan]

I need to do a ramp in verilog.......I need to start with 4hz
frequency and in 300 steps I need to have 12mhz.I need to do same
action every time but with every step my frequency must be
modified...(this is for a stepper motor acceleration)....

 

[John_H]

"Dan" <dan.costin@gmail.com> wrote in message
news:f4e089e0.0409080418.3184736@posting.google.com...

I need to do a ramp in verilog.......I need to start with 4hz
frequency and in 300 steps I need to have 12mhz.I need to do same
action every time but with every step my frequency must be
modified...(this is for a stepper motor acceleration)....

Use a high frequency clock, much greater than 12 MHz.

Either divide this master clock by a new value at each step or use a phase
accumulator where the phase value added each cycle is changed each step of
the ramp. The phase accumulator may give a better frequency match at the
higher frequencies but will also provide a little jitter. For a stepper
motor, I would suspect jitter isn't a problem.