RAM simulation (HM6116P)

[Moikel]

Hey all,

We're doing a project in college where we have to simulate a small
Motorolla 68K system which includes a RAM (HM6116P), in VHDL. However,
although the read operation is working correctly, we cannot seem to
write to the RAM. The data bus is bidirectional, and we suspect this
may have something to do with it. Here's our code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library UNISIM;
--use UNISIM.VComponents.all;

entity HM6116P is
Port ( ADDR : in std_logic_vector(7 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in std_logic;
CS : in std_logic);
end HM6116P;

architecture Behavioral of HM6116P is
subtype byte is std_logic_vector( 7 downto 0 );
type mem_matrix is array (0 to 256) of byte;

shared variable matrix:mem_matrix;
shared variable data_var: std_logic_vector (7 downto 0):="00000000";

begin

readrocess (CS,OE) is

begin

if (CS ='1') then
data_var := "ZZZZZZZZ";
else
if OE = '0' then
data_var := matrix(conv_integer(ADDR));
end if;
end if;

DATA <= data_var;

end process;

writerocess (CS,WE) is

begin

if (CS='0') then
if WE = '0' then
matrix (conv_integer(ADDR)):= DATA;
end if;
end if;

data_var:= DATA;

end process;

DATA <= data_var;

end Behavioral;
------------------------------------------------
OE , WE and CS are all active low and ADDR and DATA are the address and
data buses respectively. If somebody could help, it would be great as
our deadline is looming!

Thanks a lot,

Mike

 

[Ralf Hildebrandt]

Moikel wrote:

We're doing a project in college where we have to simulate a small
Motorolla 68K system which includes a RAM (HM6116P), in VHDL. However,
although the read operation is working correctly, we cannot seem to
write to the RAM.

readrocess (CS,OE) is

begin

if (CS ='1') then
data_var := "ZZZZZZZZ";
else
if OE = '0' then
data_var := matrix(conv_integer(ADDR));
end if;
end if;

DATA <= data_var;

end process;

You have described a latch (which is o.k. for a RAM-model), but for a
latch you need all signals, that you read in the sensitivity list
(ADDR). For the read access you get no failure, because I guess ADDR
will be stable before CS and OE will activate the process.

Hint: You don't need the additional variable data_var.
Problem: data_var is not declared as a variable inside this process.

writerocess (CS,WE) is

begin

if (CS='0') then
if WE = '0' then
matrix (conv_integer(ADDR)):= DATA;
end if;
end if;

data_var:= DATA;

end process;

DATA <= data_var;

end Behavioral;

Here is the same problem, but now it matters, that ADDR and DATA are not
in the sensitivity list.

Problem: Why do you assign a value to data_var (seems to be useless) and
then read this variable outside of this process witch is impossible,
except data_var is a shared variable. (Don't use shard variables unless
you know, what you are doing!)


Ralf

 

[Dave Pollum]

Moikel wrote:

Hey all,

We're doing a project in college where we have to simulate a small
Motorolla 68K system which includes a RAM (HM6116P), in VHDL. However,
although the read operation is working correctly, we cannot seem to
write to the RAM. The data bus is bidirectional, and we suspect this
may have something to do with it. Here's our code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library UNISIM;
--use UNISIM.VComponents.all;

entity HM6116P is
Port ( ADDR : in std_logic_vector(7 downto 0);
DATA : inout std_logic_vector(7 downto 0);
OE : in std_logic;
WE : in std_logic;
CS : in std_logic);
end HM6116P;

architecture Behavioral of HM6116P is
subtype byte is std_logic_vector( 7 downto 0 );
type mem_matrix is array (0 to 256) of byte;

shared variable matrix:mem_matrix;
shared variable data_var: std_logic_vector (7 downto 0):="00000000";

begin

readrocess (CS,OE) is

begin

if (CS ='1') then
data_var := "ZZZZZZZZ";
else
if OE = '0' then
data_var := matrix(conv_integer(ADDR));
end if;
end if;

DATA <= data_var;

end process;

writerocess (CS,WE) is

begin

if (CS='0') then
if WE = '0' then
matrix (conv_integer(ADDR)):= DATA;
end if;
end if;

data_var:= DATA;

end process;

DATA <= data_var;

end Behavioral;
------------------------------------------------
OE , WE and CS are all active low and ADDR and DATA are the address and
data buses respectively. If somebody could help, it would be great as
our deadline is looming!

Thanks a lot,

Mike

Mike;
When reading a real RAM chip, the output will be 3-stated _unless_ both
OE and CS are active (LO). so...

readrocess (CS,OE) is
begin
if CS = '0' and OE ='0' then
data_var := ... -- what you had before
else
data_var := (others => 'Z'); -- 3-states all bits
end if;
end process;

HTH
-Dave Pollum