RAM initialization

[Mario]

Hello,

I am new in VHDL and I would like to make a question.

I saw in a site a RAM code and manipulated it to make a 15 bit address an 8
bit word RAM (32k)

Is there a possible way to initialize this RAM using an external file and
how?How this file should look like?

Here is the code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RAM_32K is
port (
CLK : in std_logic;
WE : in std_logic; -- write enable
EN : in std_logic;
addr : in std_logic_vector(14 downto 0);
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0));
end RAM_32K;

architecture RAM32 of RAM_32K is
type ram_type is array(32767 downto 0) of std_logic_vector(7 downto 0);
signal ram : ram_type;
begin
process(CLK)
begin
if (CLK'event and CLK = '1') then
if (en = '1') then
if (we = '1') then
ram(conv_integer(addr)) <= datain;
dataout <= datain;
else dataout <= ram(conv_integer(addr));
end if;
end if;
end if;
end process;
end;