RAM IN VERILOG

[vogue]

we are having trouble in accessing data stored in a ram............can
anyone plz tell what is the exact syntax for accessing data stored at
various ram locations??????????????

 

[General Schvantzkoph]

On Sun, 02 May 2010 23:00:51 -0700, vogue wrote:

we are having trouble in accessing data stored in a ram............can
anyone plz tell what is the exact syntax for accessing data stored at
various ram locations??????????????

It's just an array, here is a simple async read RAM like a LUT RAM.

reg [7:0] ram[15:0];
reg [3:0] rd_addr;
reg [3:0] wr_addr;
wire [7:0] dout;

always@(posedge clk) begin
if(write) begin
ram[wr_addr] <= din;
end
end

assign dout = ram[rd_addr];