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If it is 64x8 then you store it in 64 clock cycles. OtherwisePlease help me if any possibility is there to solve this.
I have 64 byte data in one register.
I have to store all data into one 64x8 RAM in one clock cycle.
-- glenI need to write verilog coding for this.
64x8 => 1x512 (not 1x256)mahesh<mahesh.vtr@gmail.com> wrote:
Please help me if any possibility is there to solve this.
I have 64 byte data in one register.
I have to store all data into one 64x8 RAM in one clock cycle.
If it is 64x8 then you store it in 64 clock cycles. Otherwise
you want a 1x256 RAM, which may exist in verilog, but they
are hard to find in the store.
I need to write verilog coding for this.
-- glen
A Verilog description of a 64 x 8 RAM does not preclude writingOn 09/09/2010 23:03, glen herrmannsfeldt wrote:
mahesh<mahesh....@gmail.com> wrote:
Please help me if any possibility is there to solve this.
I have 64 byte data in one register.
I have to store all data into one 64x8 RAM in one clock cycle.
If it is 64x8 then you store it in 64 clock cycles. Otherwise
you want a 1x256 RAM, which may exist in verilog, but they
are hard to find in the store.
I need to write verilog coding for this.
-- glen
64x8 => 1x512 (not 1x256)
Claude.
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I do tend to think about the ability to implement somethingA Verilog description of a 64 x 8 RAM does not preclude writing
it in a single clock cycle. You can use a "for" loop to do this
very easily. It doesn't really turn into a "1 x 512 RAM" until
after synthesis.
You probably don't want a combinatorial divider, but dual-edge flopsgabor <ga...@alacron.com> wrote:
(snip)
A Verilog description of a 64 x 8 RAM does not preclude writing
it in a single clock cycle. You can use a "for" loop to do this
very easily. It doesn't really turn into a "1 x 512 RAM" until
after synthesis.
I do tend to think about the ability to implement something
in actual logic pretty early. Note, though, that there are things
that can be implemented but that synthesis tools won't allow.
Most won't divide by a variable, yet a (slow and big) combinatorial
divider can be implemented in most logic families.
They won't synthesize a FF that clocks on both edges, (not counting
the DDR double FF), as those don't exist in logic.
-- glen