Race in hierarchical access?

[Neo]

HI,
Is there any scope for race occurring in doing hierarchical access? I
ask this as I am seeing the foll happen-

always(poseddge clk, negedge rst)
if (rst)
---
---
else
if(wr and acs)
r_data <= p_data;
----
----
end
In above I see that r_data is changing simultaneously with 'wr' going
high. and it erroneously senses wr high for 2 cycles even though it is
high for one cycle only. I suspect this might be due to race as all
the signals in the above always blk including clk and rst are
hierarchically referenced from a module but a single module. Is this
due to race?
If so how do I overcome this, register the values?


Thanks,
Neo

 

[devices]

"Neo" <zingafriend@yahoo.com> wrote in message
news:1186999867.559942.77470@r34g2000hsd.googlegroups.com...

HI,
Is there any scope for race occurring in doing hierarchical access? I
ask this as I am seeing the foll happen-

always(poseddge clk, negedge rst)
if (rst)
---
---
else
if(wr and acs)
r_data <= p_data;
----
----
end
In above I see that r_data is changing simultaneously with 'wr' going
high. and it erroneously senses wr high for 2 cycles even though it is
high for one cycle only. I suspect this might be due to race as all
the signals in the above always blk including clk and rst are
hierarchically referenced from a module but a single module. Is this
due to race?
If so how do I overcome this, register the values?


Thanks,
Neo

turn your "always sensitivity list" into:

always @(posedge clk or negedge rst)

"and"

if(wr and acs) into

if (wr & acs)

 

[Neo]

On Aug 13, 5:00 pm, "devices" <me@home> wrote:

"Neo" <zingafri...@yahoo.com> wrote in message

news:1186999867.559942.77470@r34g2000hsd.googlegroups.com...



HI,
Is there any scope for race occurring in doing hierarchical access? I
ask this as I am seeing the foll happen-

always(poseddge clk, negedge rst)
if (rst)
---
---
else
if(wr and acs)
r_data <= p_data;
----
----
end
In above I see that r_data is changing simultaneously with 'wr' going
high. and it erroneously senses wr high for 2 cycles even though it is
high for one cycle only. I suspect this might be due to race as all
the signals in the above always blk including clk and rst are
hierarchically referenced from a module but a single module. Is this
due to race?
If so how do I overcome this, register the values?

Thanks,
Neo

turn your "always sensitivity list" into:

always @(posedge clk or negedge rst)

"and"

if(wr and acs) into

if (wr & acs)

I am sorry for mixing vhdl syntax here but yes that is what is there,
now please to my question...

 

[Mike Treseler]

Neo wrote:

always(poseddge clk, negedge rst)
if (rst)
---
else
if(wr and acs)
r_data <= p_data;
----
end
In above I see that r_data is changing simultaneously with 'wr' going
high.

You have inferred a clock-enabled register
with wr & acs as the enable input.

and it erroneously senses wr high for 2 cycles even though it is
high for one cycle only.

A clock enable input should be a synchronized strobe
rather than a combinational input.
Here is a related example:

http://home.comcast.net/~mike_treseler/count_enable.v

-- Mike Treseler