race conditions/pulse width

T

The Weiss Family

Guest
The "Clock Edge Transitions" thread got me thinking.
If I have two synchronous processes, one of which outputs a signal
synchronous to a clock and is a single clock in width, and the other process
monitors the status of the signal, is it possible that the pulse could occur
without the second process seeing it?
I have code in a design that seems to work fine, but I have doubts that this
is not the best way of doing things...
See the example below:

PROC_A: process(clk, rst)
begin
-- async reset, set to zero
if (rst = '1') then
pulse <= '0';

-- at each rising edge, set pulse to '1'
elsif (rising_edge(clk)) then
if (pulse <= '1') then -- here always limit pulse to 1 clock.
That is, if it is '1', set it right back to '0' on the next clock
pulse <= '0';

elsif (some_condition_is_true)
pulse < = '1';
endif;
endif;
end process;

PROC_B: process(clk, rst)
begin
-- async reset, set to zero
if (rst = '1') then
pulse2 <= '0';

elsif (rising_edge(clk)) then
if (pulse = '1') then -- is it possible that this process will
never see pulse = '1' because it is only 1 clock wide?
pulse2 <= '1'
end if;
end process;
 
The Weiss Family wrote:

The "Clock Edge Transitions" thread got me thinking.
If I have two synchronous processes, one of which outputs a signal
synchronous to a clock and is a single clock in width, and the other
process monitors the status of the signal, is it possible that the
pulse could occur without the second process seeing it?
Click to expand...
No. Remember that there always is a delta cycle delay in any signal
assignment.

So the watching process will not see the new value at the same clock
edge, because that value is not there yet (it will happen one delta
cycle in the future).

At the next clock edge it will see the new value, which is going to
stay for just another delta cycle. So your pulse of one clock period
will not be missed.

Think in hardware. The output of a flip-flop changes after the clock
edge. Another flip-flop on the same clock clocks in the "old" value
at the same clock edge and the "new" value on the next clock edge.

Paul.
 
"Paul Uiterlinden" <paulu@sx4all.nl> wrote in message
news:41718c51$0$36860$e4fe514c@news.xs4all.nl...
The Weiss Family wrote:

The "Clock Edge Transitions" thread got me thinking.
If I have two synchronous processes, one of which outputs a signal
synchronous to a clock and is a single clock in width, and the other
process monitors the status of the signal, is it possible that the
pulse could occur without the second process seeing it?

No. Remember that there always is a delta cycle delay in any signal
assignment.

So the watching process will not see the new value at the same clock
edge, because that value is not there yet (it will happen one delta
cycle in the future).

At the next clock edge it will see the new value, which is going to
stay for just another delta cycle. So your pulse of one clock period
will not be missed.

Think in hardware. The output of a flip-flop changes after the clock
edge. Another flip-flop on the same clock clocks in the "old" value
at the same clock edge and the "new" value on the next clock edge.

Paul.
Click to expand...
I guess I was thinking that the pulse could potentially be a glitch.
That is, in terms of hardware, if the pulse signal was exactly one clock,
and it lined up just right, it could violate a setup/hold time and
potentially be missed by the observing flop. Is this something to worry
about?
 
In article <10n39jv2hrjim85@corp.supernews.com>,
The Weiss Family <weissfamily97@charter.net> wrote:
[...]
I guess I was thinking that the pulse could potentially be a glitch.
That is, in terms of hardware, if the pulse signal was exactly one clock,
and it lined up just right, it could violate a setup/hold time and
potentially be missed by the observing flop. Is this something to worry
about?
Click to expand...
The biggest worry in hardware is whether the signal is ready for the next
clock in time.

Only when you have a clock skew issue, do you need to worry about
interactions on the same edge.

--
--
kensmith@rahul.net forging knowledge
 
On Sat, 16 Oct 2004, Paul Uiterlinden wrote:

The Weiss Family wrote:

The "Clock Edge Transitions" thread got me thinking.
If I have two synchronous processes, one of which outputs a signal
synchronous to a clock and is a single clock in width, and the other
process monitors the status of the signal, is it possible that the
pulse could occur without the second process seeing it?

No. Remember that there always is a delta cycle delay in any signal
assignment.

So the watching process will not see the new value at the same clock
edge, because that value is not there yet (it will happen one delta
cycle in the future).

At the next clock edge it will see the new value, which is going to
stay for just another delta cycle. So your pulse of one clock period
will not be missed.

Think in hardware. The output of a flip-flop changes after the clock
edge. Another flip-flop on the same clock clocks in the "old" value
at the same clock edge and the "new" value on the next clock edge.

Paul.

I agree with Paul. While the pulse will not be missed, it will be read
Click to expand...
only at the next clock edge,when it will be a "old" value.
 
"Paul Uiterlinden" <paulu@sx4all.nl> wrote in message
news:41718c51$0$36860$e4fe514c@news.xs4all.nl...
The Weiss Family wrote:

The "Clock Edge Transitions" thread got me thinking.
If I have two synchronous processes, one of which outputs a signal
synchronous to a clock and is a single clock in width, and the other
process monitors the status of the signal, is it possible that the
pulse could occur without the second process seeing it?

No. Remember that there always is a delta cycle delay in any signal
assignment.

So the watching process will not see the new value at the same clock
edge, because that value is not there yet (it will happen one delta
cycle in the future).

At the next clock edge it will see the new value, which is going to
stay for just another delta cycle. So your pulse of one clock period
will not be missed.

Think in hardware. The output of a flip-flop changes after the clock
edge. Another flip-flop on the same clock clocks in the "old" value
at the same clock edge and the "new" value on the next clock edge.

Paul.
Click to expand...
Good!
I think everyone concurs that I don't have to change my design!
Thanks for the input.

Adam
 
The one thing that you can do wrong here is
to mess with clock. Lets suppose you merge two
designs and one uses the name Clk and the other
Clock for the same signal. Make sure to fix it
by changing the names and not by doing:

Clock <= Clk ; -- bad: clocks not delta cycle aligned.

Note in your second ff I changed Clk to Clock.


PROC_A: process(clk, rst)
begin
-- async reset, set to zero
if (rst = '1') then
pulse <= '0';

-- at each rising edge, set pulse to '1'
elsif (rising_edge(clk)) then
if (pulse <= '1') then -- here always limit pulse to 1 clock.
That is, if it is '1', set it right back to '0' on the next clock
pulse <= '0';

elsif (some_condition_is_true)
pulse < = '1';
endif;
endif;
end process;

PROC_B: process(clk, rst)
begin
-- async reset, set to zero
if (rst = '1') then
pulse2 <= '0';
Click to expand...
elsif (rising_edge(CLOCK)) then
-- This would be bad: ^^^^^^

if (pulse = '1') then -- is it possible that this process will
never see pulse = '1' because it is only 1 clock wide?
pulse2 <= '1'
end if;
end process;
Click to expand...
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top