race condition

[sridhar]

I guess there is a race condition with this

module y(a);
$display("%b",a);
endmodule
module x;
reg a;
initial
a = 1;
y y1(a);
endmodule

Would this avoid the race condition?

module x;
reg a;
initial
#0
a = 1;
y y1(a);
endmodule

Thanks
sridhar

 

[Ajeetha Kumari]

Hi Sridhar,
Yes that would avoid the race condition, but you will get your
display output as "1'bx" - was that intended?

Ajeetha,
http://www.noveldv.com
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition.

v_sridhar@mailcity.com (sridhar) wrote in message news:<7492ef5f.0404191615.7fa62def@posting.google.com>...

I guess there is a race condition with this

module y(a);
$display("%b",a);
endmodule
module x;
reg a;
initial
a = 1;
y y1(a);
endmodule

Would this avoid the race condition?

module x;
reg a;
initial
#0
a = 1;
y y1(a);
endmodule

Thanks
sridhar

 

[sridhar]

aji@noveldv.com (Ajeetha Kumari) wrote in message news:<8df95881.0404231015.3c184369@posting.google.com>...

Hi Sridhar,
Yes that would avoid the race condition, but you will get your
display output as "1'bx" - was that intended?

Ajeetha,
http://www.noveldv.com
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition.

Thanks for the reply. I saw this code in a verilog book. I guess this
involves a race condition involving enable_reg.Can anyone confirm?

module m(clk);
input clk;
wire enable_reg;
reg r,state;

initial state = 0;
always @(posedge clk)
r = (enable_reg)1:0;

always @(posedge clk)
state = (state == 0)?1:0;
assign enable_reg = state;

endmodule
Thanks
sridhar

 

[Larry Doolittle]

In article <7492ef5f.0404251409.326f2b2d@posting.google.com>, sridhar wrote:

aji@noveldv.com (Ajeetha Kumari) wrote ...

I saw this code in a verilog book. I guess this
involves a race condition involving enable_reg.Can anyone confirm?

module m(clk);
input clk;
wire enable_reg;
reg r,state;

initial state = 0;
always @(posedge clk)
r = (enable_reg)1:0;

Yeesh.
1. I assume you transcribed it wrong, and it's really
r = (enable_reg)?1:0;
2. This looks like it was in turn translated from VHDL.
Verilog doesn't make you jump through hoops to turn
from boolean to numeric. It might just as well be
r = enable_reg;
3. This construct is supposed to represent a clocked
update of a register. To make the semantics work
precisely, including avoidance of the potential race,
trade the "=" (blocking assignment) for "<=" (non-
blocking assignment), like this:
r <= enable_reg;

always @(posedge clk)
state = (state == 0)?1:0;

Ditto (well, 2 and 3 anyway):
state <= (state == 0);
or even
state <= ~state;

assign enable_reg = state;

This much is fine, although this contrived example would
be shorter and equivalent if you just substituted enable_reg
with state, and cut the number of "variables" by one.

endmodule

- Larry