R: useless synthetized blocks

[Max]

On 18 Sep 2003 00:17:46 -0700
cialdi@firenze.net (Max) wrote:

I tried to implement a decoder in two differnet way:
--------------8<-------------------------
entity main is
Generic (w : integer := 12);
Port ( addr : in std_logic_vector(3 downto 0);
ce : in std_logic;
y : out std_logic_vector(w-1 downto 0));
end main;

architecture Behavioral of main is

begin

-- first way
process (addr, ce)
begin
y <= (others => '0');
if (addr < w and ce = '1') then
y(to_integer(unsigned(addr))) <= '1';
end if;
end process;

[...]
I prefer the firsr version since I don't need to rewrite the code if
generic 'w' changes.
After synthesis the device utilization is exacly the same, but looking
at rtl schematics (I use xilinx webpack ise) there is a differce:
in the first way is synthetized a comparator. This is correct but
useless since the other logic can provide its function.

there is another way to avoid the presence of comparator?
And why the tool synthetize a 5bit comparator instead of 4bit as I am

especting?

Here is the report:
=======================================================================
== HDL Synthesis Report

Macro Statistics
# Comparators : 1
5-bit comparator less : 1

thanks

 

[Jim Lewis]

Max,
The synthesis tool sees Addr < w a comparitor.
It is probably 5 bits as it incorporates the
ce = '1' into a single comparitor.

Is it valid for ce='1' and addr be greater than w?
If not, it is safe to code:

if (ce = '1') then
y(to_integer(unsigned(addr))) <= '1';
end if;

If the circuit is broken and addr > w occurs when
ce='1', then a VHDL simulator will detect an out
of range index and generate a run time error.
If this is unacceptable, see Dan RADUT's reply
to your previous post.

Cheers,
Jim Lewis

Max wrote:

On 18 Sep 2003 00:17:46 -0700
cialdi@firenze.net (Max) wrote:


I tried to implement a decoder in two differnet way:
--------------8<-------------------------
entity main is
Generic (w : integer := 12);
Port ( addr : in std_logic_vector(3 downto 0);
ce : in std_logic;
y : out std_logic_vector(w-1 downto 0));
end main;

architecture Behavioral of main is

begin

-- first way
process (addr, ce)
begin
y <= (others => '0');
if (addr < w and ce = '1') then
y(to_integer(unsigned(addr))) <= '1';
end if;
end process;


[...]

I prefer the firsr version since I don't need to rewrite the code if
generic 'w' changes.
After synthesis the device utilization is exacly the same, but looking
at rtl schematics (I use xilinx webpack ise) there is a differce:
in the first way is synthetized a comparator. This is correct but
useless since the other logic can provide its function.

there is another way to avoid the presence of comparator?

And why the tool synthetize a 5bit comparator instead of 4bit as I am
especting?

Here is the report:
=======================================================================
== HDL Synthesis Report

Macro Statistics
# Comparators : 1
5-bit comparator less : 1

thanks

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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