R: again on state machine

[Max]

On Wed, 10 Sep 2003 21:50:51 +1000
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

The basic problem is that you are using two clocks (start and clk) on
the same flip flops. This probably isn't what you wanted, and will
cause the synthesiser to barf.

I suggest you rethink your design. You also might like to google for
"vhdl clocked process template".

Does it really need to be sensitive to the rising edge of start? The
problem is much simpler if you can sample start with a flip flop (i.e.
it goes into the D input, not the Clk input).

If you really need to trigger on the edge of start (perhaps because it
has a pulse width that's smaller than the period of clk) then this
should be done with a separate flip flop that produces a longer signal
that your state machine can sample.
the falling edge of my start signal can occur before my state machine

ends its elaboration, but can also occur after. So I cannot use the
start level.

thanks