quick question

[FP]

I have an input pulse which can be high for more than one clock cycle.

I want to stay in wait state after i detect the posedge and switch to
armed state after i detect the negative edge. How do I do this in
verilog? I dont want to use wait statements as they are not
synthesizable. I am using an FSM to do this. I have tried using if
statements but it wont work.

Thanks in advance

 

[beky4kr@gmail.com]

On 23 מאי, 16:42, FP <FPGA.unkn...@gmail.com> wrote:

I have an input pulse which can be high for more than one clock cycle.

I want to stay in wait state after i detect the posedge and switch to
armed state after i detect the negative edge. How do I do this in
verilog? I dont want to use wait statements as they are not
synthesizable. I am using an FSM to do this. I have tried using if
statements but it wont work.

Thanks in advance

You need to detect edges by sampling the signal.
Here is an example (part of the code is available from my site as an
SDIO project http://bknpk.no-ip.biz/)

//One output stream to calculate CRC.
//One output stream for SD data out.
reg start_q;
...
//timing counter
assign cnt_i (start && !start_q && size) ? 8'd137 :
(start && !start_q && !size) ? 8'd49 :
(|cnt_q) ? (cnt_q - 8'd1) :
cnt_q;
...
always @ (posedge clk or posedge rst) begin
if(rst) begin
cnt_q <= 8'h0;
start_q <= 1'b0;
...
end else begin
cnt_q <= cnt_i;
start_q <= start;

So by asking on start && !start_q a posedge is detected.