quick estimates of power and area for typical VLSI circuits

[Choudhary]

Hi,
Could you please let me know where can I get quick
estimates/approximate analytical formulae of power,delay and area of
typical VLSI circuits such as (adders,mutipliers FIFOs ,SRAM )?

The process is 0.13 micron.

Regards,
Choudhary

 

[Kelvin]

You may rephrase your question more specific, for example,

Given at 20MHz & 0.13um CMOS, what is the estimated power, area of an 8*8
adder/multiplier, an 8*128 FIFO, etc...
Experienced engineers may tell you some rough estimate...

Kelvin




"Choudhary" <kiran_krishna_choudhary@yahoo.com> wrote in message
news:470b6539.0309111954.5d4ecfa1@posting.google.com...

Hi,
Could you please let me know where can I get quick
estimates/approximate analytical formulae of power,delay and area of
typical VLSI circuits such as (adders,mutipliers FIFOs ,SRAM )?

The process is 0.13 micron.

Regards,
Choudhary

 

[Choudhary]

Thanks for the reply.
I need estimates at 500 MHz and 1GHz.Voltage :1.2 volts. CMOS process.
The circuits I am interested in are for a 5 bit data path.
1.adder 5 by 5 bit CLA adder.
2.FIFO 5 bit and length is 36
3.SRAM cell of size 128 elements. each is 5 bit wide.
4.a simple register of 5 bit word.

Regards,
Choudhary

"Kelvin" <andydee_2003@hotmail.com> wrote in message news:<bjus25$c5t$1@reader01.singnet.com.sg>...

You may rephrase your question more specific, for example,

Given at 20MHz & 0.13um CMOS, what is the estimated power, area of an 8*8
adder/multiplier, an 8*128 FIFO, etc...
Experienced engineers may tell you some rough estimate...

Kelvin




"Choudhary" <kiran_krishna_choudhary@yahoo.com> wrote in message
news:470b6539.0309111954.5d4ecfa1@posting.google.com...
Hi,
Could you please let me know where can I get quick
estimates/approximate analytical formulae of power,delay and area of
typical VLSI circuits such as (adders,mutipliers FIFOs ,SRAM )?

The process is 0.13 micron.

Regards,
Choudhary

 

[Uncle Noah]

kiran_krishna_choudhary@yahoo.com (Choudhary) wrote in message news:<470b6539.0309151410.7e705ab4@posting.google.com>...

Thanks for the reply.
I need estimates at 500 MHz and 1GHz.Voltage :1.2 volts. CMOS process.
The circuits I am interested in are for a 5 bit data path.
1.adder 5 by 5 bit CLA adder.
2.FIFO 5 bit and length is 36
3.SRAM cell of size 128 elements. each is 5 bit wide.
4.a simple register of 5 bit word.

Regards,
Choudhary

These questions are so implementation specific. I don't think it is
convenient for as to answer this.

Some of easy stuff is:
5-bit CLA adder: 30-35 gates
SRAM cell 128x5: whatever says your SRAM generator
the rest: perform synthesis, buy some RTL or gate-level power
estimation tool or work with analytical models (Mulder for area,
Rabaey for capacitance (to calc. power) and so on).

Maybe some *sucker* will become your loyal servant and help you on
this extensive work.

Regards
Uncle "The G.B. Man" Noah