P
Peng Yu
Guest
Hi,
Synopsys document "Behavioral Compiler Verilog User and Modeling
Guide" states some behavioral coding guidelines. It's easy to know the
reasons of some rules. But it's hard for me to figure out the reasons
of the others.
In particular, I don't understand Chapter 11's General Coding Rule 5
& 6.
Rule 5 read as "Place at least one clock statement after the last
write inside a loop and before a loop continue or exit".
Rule 6 read as "Place at least one clock statement after the last
write before a loop".
An example for Rule 5 & 6 is listed below.
/*************************************/
re <= (a * c * d);
@(posedge clk);
if (reset == 1) disable reset_loop;
begin: for_loop1
for (i = 0; i < 12; i = i + 1)
begin:for_loop_label
re <= (a * c * d + i);
@(posedge clk);
if (reset == 1) disable reset_loop;
im <= (c * d);
@(posedge clk);
if (reset == 1) disable reset_loop;
end
end
/**********************************/
I wonder whether I should follow Rule 5&6 in this example. Because
I can change the previous code to the following. The rules change to
"Place at least one clock statement before the first write inside a
loop" and "Place at least one clock statement before the first write
after a loop".
/*************************************/
re <= (a * c * d);
begin: for_loop1
for (i = 0; i < 12; i = i + 1)
begin:for_loop_label
@(posedge clk);
if (reset == 1) disable reset_loop;
re <= (a * c * d + i);
@(posedge clk);
if (reset == 1) disable reset_loop;
im <= (c * d);
end
end
@(posedge clk);
if (reset == 1) disable reset_loop;
/*************************************/
Best wishes,
Peng
PS:
The "clock statement" means something like this:
@(posedge clk);
if (reset == 1) disable reset_loop;
Synopsys document "Behavioral Compiler Verilog User and Modeling
Guide" states some behavioral coding guidelines. It's easy to know the
reasons of some rules. But it's hard for me to figure out the reasons
of the others.
In particular, I don't understand Chapter 11's General Coding Rule 5
& 6.
Rule 5 read as "Place at least one clock statement after the last
write inside a loop and before a loop continue or exit".
Rule 6 read as "Place at least one clock statement after the last
write before a loop".
An example for Rule 5 & 6 is listed below.
/*************************************/
re <= (a * c * d);
@(posedge clk);
if (reset == 1) disable reset_loop;
begin: for_loop1
for (i = 0; i < 12; i = i + 1)
begin:for_loop_label
re <= (a * c * d + i);
@(posedge clk);
if (reset == 1) disable reset_loop;
im <= (c * d);
@(posedge clk);
if (reset == 1) disable reset_loop;
end
end
/**********************************/
I wonder whether I should follow Rule 5&6 in this example. Because
I can change the previous code to the following. The rules change to
"Place at least one clock statement before the first write inside a
loop" and "Place at least one clock statement before the first write
after a loop".
/*************************************/
re <= (a * c * d);
begin: for_loop1
for (i = 0; i < 12; i = i + 1)
begin:for_loop_label
@(posedge clk);
if (reset == 1) disable reset_loop;
re <= (a * c * d + i);
@(posedge clk);
if (reset == 1) disable reset_loop;
im <= (c * d);
end
end
@(posedge clk);
if (reset == 1) disable reset_loop;
/*************************************/
Best wishes,
Peng
PS:
The "clock statement" means something like this:
@(posedge clk);
if (reset == 1) disable reset_loop;
