M
Mike Treseler
Guest
Not that I know of. See the fine print on the web page.Questions about single process coding style from JaysonL
Reference link
http://home.comcast.net/~mike_treseler/
Q1: Have the single process coding style been synthesized with synopsys tools?
The synthesis is correct.I tried to synthesis the Uart example with Synopsys Design_Analyzer but failure.
A error message try to use synchronized value.
Dose synopsys not support this coding style or just my tool is too old, 2005 version?
Q2: What does the warning message in Xilinx ise mean?
I synthesized the UART example with ISE7.1 successfully,
but a lot of warning messages for variables in design.
The warning message is Potential simulation mismatch,
variable ABC declared in block A is assigned in block B.
What is the risk in this warning?
The warnings are inappropriate in my opinion.
Quartus makes no such warnings.
It has been tested on Modelsim, and NC-Sim.Q3: Does the testbench in reference link work?
For ISE, the testbench was only tested on the modelsim simulator.I try simulation the Uart example but it wouldnt run.
The error message is Simulator:222 - Generated C++ compilation was unsuccessful.
Is my ISE7.1 is too old or there is errors in testbench?
Could someone please fix it for ISE7.1?
Q4: Has The Uart example passed post_synthesis simulation?
Yes.
Thanks for any informantion
JaysonL