question when using asmi_parallel ip core

P

PaulHam

Guest
Hi,all

I'm Paul Ham in Korea and have some difficulties in using ASMI_PARALLE
altera ip core.
Anyone who knows well this problem could advice to me.

I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without service pack.
My design is very simple like below :
1) receive the data from PC via RS232.
The data is .rpd file made by Conver Programming Files of Quartus menu.
Due to the EPCS spec, its size is 512KByte.
2) write the data to internal dpram. (double buffering)
3) read the data from dpram to asmi_parallel every 256 bytes.(page write)

When I simulated it with signaltap, it wrote other .rpd file into EPCS
well.
And it configured well after power-up.

But it didn't work when I programmed itself directly to EPCS4.
It always generate the illegal_erase and illegal_write.

I found some ways to solve the problem like below but anything didn't wor
well.
1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE A
REGULAR IO" at .qsf file.
-> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE A
REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE A
REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE A
REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATIO
"USE AS REGULAR IO"
2) modify the value of "ncs_reg" in asmi_parallel.v as below.
-> always @ ( negedge clkin_wire or posedge end_ophdly)
if (end_ophdly == 1'b1) ncs_reg <= 1'b1;
else if (wire_ncs_reg_ena == 1'b1) ncs_reg <= 1'b0;
3) install the service pack 1 : I didn't try it

I guess that the problem is related to the setting of 4 configuratio
pins.
But I'm not sure what could I do.
If you have any advice or solution, please let me know.

Thanks advance
Regards
Paul




---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi Paul,

First of all try to use Indirect flash programming using jtag interface.
If it will work fine your EPCS is connected correctly and your fpga
should start automatically.
If not , check epcs connection to fpga and msel pins configuration.

Second step is to write and read back epcs config using your rs connection.

Then you have to prepare flash image using
sof2flash" --epcs --input="example.sof" --output="example.flash"

Adam

Hi,all

I'm Paul Ham in Korea and have some difficulties in using ASMI_PARALLEL
altera ip core.
Anyone who knows well this problem could advice to me.

I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without service pack.
My design is very simple like below :
1) receive the data from PC via RS232.
The data is .rpd file made by Conver Programming Files of Quartus menu.
Due to the EPCS spec, its size is 512KByte.
2) write the data to internal dpram. (double buffering)
3) read the data from dpram to asmi_parallel every 256 bytes.(page write)

When I simulated it with signaltap, it wrote other .rpd file into EPCS4
well.
And it configured well after power-up.

But it didn't work when I programmed itself directly to EPCS4.
It always generate the illegal_erase and illegal_write.

I found some ways to solve the problem like below but anything didn't work
well.
1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE AS
REGULAR IO" at .qsf file.
-> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION
"USE AS REGULAR IO"
2) modify the value of "ncs_reg" in asmi_parallel.v as below.
-> always @ ( negedge clkin_wire or posedge end_ophdly)
if (end_ophdly == 1'b1) ncs_reg<= 1'b1;
else if (wire_ncs_reg_ena == 1'b1) ncs_reg<= 1'b0;
3) install the service pack 1 : I didn't try it

I guess that the problem is related to the setting of 4 configuration
pins.
But I'm not sure what could I do.
If you have any advice or solution, please let me know.

Thanks advance
Regards
Paul




---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
 
Hi Paul,

Any progress ?

Adam

Hi Paul,

First of all try to use Indirect flash programming using jtag interface.
If it will work fine your EPCS is connected correctly and your fpga
should start automatically.
If not , check epcs connection to fpga and msel pins configuration.

Second step is to write and read back epcs config using your rs connection.

Then you have to prepare flash image using
sof2flash" --epcs --input="example.sof" --output="example.flash"

Adam

Hi,all

I'm Paul Ham in Korea and have some difficulties in using ASMI_PARALLEL
altera ip core.
Anyone who knows well this problem could advice to me.

I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without service pack.
My design is very simple like below :
1) receive the data from PC via RS232.
The data is .rpd file made by Conver Programming Files of Quartus menu.
Due to the EPCS spec, its size is 512KByte.
2) write the data to internal dpram. (double buffering)
3) read the data from dpram to asmi_parallel every 256 bytes.(page write)

When I simulated it with signaltap, it wrote other .rpd file into EPCS4
well.
And it configured well after power-up.

But it didn't work when I programmed itself directly to EPCS4.
It always generate the illegal_erase and illegal_write.

I found some ways to solve the problem like below but anything didn't
work
well.
1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE AS
REGULAR IO" at .qsf file.
-> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION
"USE AS REGULAR IO"
2) modify the value of "ncs_reg" in asmi_parallel.v as below.
-> always @ ( negedge clkin_wire or posedge end_ophdly)
if (end_ophdly == 1'b1) ncs_reg<= 1'b1;
else if (wire_ncs_reg_ena == 1'b1) ncs_reg<= 1'b0;
3) install the service pack 1 : I didn't try it

I guess that the problem is related to the setting of 4 configuration
pins.
But I'm not sure what could I do.
If you have any advice or solution, please let me know.

Thanks advance
Regards
Paul




---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
 
I'm really sorry for late reply about your help.
A few days ago, I've installed the service pack 1(SP1) as someone'
comment.
And then I made a new project with same source ion the SP1.
Surprisingly, everything worked fine !!

I quess that someting keeps the lock on the configuration pins on th
user-mode at no service pack version.
But I don't know the exact cause.

Anyway, a little bit late, I appreciate you, Adam.

If you know the usage of "asmi_parallel" ip core, I'd like get some advice
about using "write operation".
There are two kind of write operation as below.
1) single byte write operation
2) page write operation (2~256 byte)
When I used the page write operation with 256 byte PAGE_SIZE,
the "busy" signal (it's "doing" output from asmi_parallel ip core) keeps
"high" during 30us after write command.
Strangely, when I tried to use single byte write operation,
the "busy" signal keeps "high" during 300us after write command !!
I cannot believe it and its time is different from the data sheet.
On the data sheet, the "busy" high time is shown as about 3 us on th
single
byte write operation..

It bothers me not to select actual write operation at this time.
If you have advice for me, please donot hesitate.
Thanks in advanced
Regards
Paul






Hi Paul,

Any progress ?

Adam

Hi Paul,

First of all try to use Indirect flash programming using jta
interface.
If it will work fine your EPCS is connected correctly and your fpga
should start automatically.
If not , check epcs connection to fpga and msel pins configuration.

Second step is to write and read back epcs config using your r
connection.

Then you have to prepare flash image using
sof2flash" --epcs --input="example.sof" --output="example.flash"

Adam

Hi,all

I'm Paul Ham in Korea and have some difficulties in usin
ASMI_PARALLEL
altera ip core.
Anyone who knows well this problem could advice to me.

I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without servic
pack.
My design is very simple like below :
1) receive the data from PC via RS232.
The data is .rpd file made by Conver Programming Files of Quartu
menu.
Due to the EPCS spec, its size is 512KByte.
2) write the data to internal dpram. (double buffering)
3) read the data from dpram to asmi_parallel every 256 bytes.(pag
write)

When I simulated it with signaltap, it wrote other .rpd file int
EPCS4
well.
And it configured well after power-up.

But it didn't work when I programmed itself directly to EPCS4.
It always generate the illegal_erase and illegal_write.

I found some ways to solve the problem like below but anything didn't
work
well.
1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE AS
REGULAR IO" at .qsf file.
-> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "US
AS
REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION
"USE AS REGULAR IO"
2) modify the value of "ncs_reg" in asmi_parallel.v as below.
-> always @ ( negedge clkin_wire or posedge end_ophdly)
if (end_ophdly == 1'b1) ncs_reg<= 1'b1;
else if (wire_ncs_reg_ena == 1'b1) ncs_reg<= 1'b0;
3) install the service pack 1 : I didn't try it

I guess that the problem is related to the setting of 4 configuration
pins.
But I'm not sure what could I do.
If you have any advice or solution, please let me know.

Thanks advance
Regards
Paul




---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
---------------------------------------
Posted through http://www.FPGARelated.com
 
I can't cause I used NIOS & C library to do remote update ( Quartus II
7.0 ). Sorry I can't help you with this IP.

BR

Adam


I'm really sorry for late reply about your help.
A few days ago, I've installed the service pack 1(SP1) as someone's
comment.
And then I made a new project with same source ion the SP1.
Surprisingly, everything worked fine !!

I quess that someting keeps the lock on the configuration pins on the
user-mode at no service pack version.
But I don't know the exact cause.

Anyway, a little bit late, I appreciate you, Adam.

If you know the usage of "asmi_parallel" ip core, I'd like get some advice
about using "write operation".
There are two kind of write operation as below.
1) single byte write operation
2) page write operation (2~256 byte)
When I used the page write operation with 256 byte PAGE_SIZE,
the "busy" signal (it's "doing" output from asmi_parallel ip core) keeps
"high" during 30us after write command.
Strangely, when I tried to use single byte write operation,
the "busy" signal keeps "high" during 300us after write command !!
I cannot believe it and its time is different from the data sheet.
On the data sheet, the "busy" high time is shown as about 3 us on the
single
byte write operation..

It bothers me not to select actual write operation at this time.
If you have advice for me, please donot hesitate.
Thanks in advanced
Regards
Paul






Hi Paul,

Any progress ?

Adam

Hi Paul,

First of all try to use Indirect flash programming using jtag
interface.
If it will work fine your EPCS is connected correctly and your fpga
should start automatically.
If not , check epcs connection to fpga and msel pins configuration.

Second step is to write and read back epcs config using your rs
connection.

Then you have to prepare flash image using
sof2flash" --epcs --input="example.sof" --output="example.flash"

Adam

Hi,all

I'm Paul Ham in Korea and have some difficulties in using
ASMI_PARALLEL
altera ip core.
Anyone who knows well this problem could advice to me.

I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without service
pack.
My design is very simple like below :
1) receive the data from PC via RS232.
The data is .rpd file made by Conver Programming Files of Quartus
menu.
Due to the EPCS spec, its size is 512KByte.
2) write the data to internal dpram. (double buffering)
3) read the data from dpram to asmi_parallel every 256 bytes.(page
write)

When I simulated it with signaltap, it wrote other .rpd file into
EPCS4
well.
And it configured well after power-up.

But it didn't work when I programmed itself directly to EPCS4.
It always generate the illegal_erase and illegal_write.

I found some ways to solve the problem like below but anything didn't
work
well.
1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE AS
REGULAR IO" at .qsf file.
-> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE
AS
REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS
REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION
"USE AS REGULAR IO"
2) modify the value of "ncs_reg" in asmi_parallel.v as below.
-> always @ ( negedge clkin_wire or posedge end_ophdly)
if (end_ophdly == 1'b1) ncs_reg<= 1'b1;
else if (wire_ncs_reg_ena == 1'b1) ncs_reg<= 1'b0;
3) install the service pack 1 : I didn't try it

I guess that the problem is related to the setting of 4 configuration
pins.
But I'm not sure what could I do.
If you have any advice or solution, please let me know.

Thanks advance
Regards
Paul




---------------------------------------
Posted through http://www.FPGARelated.com




---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
 
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