K
Kelvin, Chee
Guest
Hi, there:
I am reading the sample design in XAPP290, regarding the partial
reconfiguration of Vertex class FPGAs.
I want to know what is the purpose of the Assembly, it seems to me, after
assembly, all three bit streams
are same 42Kb, meaning the full length.
I feel that, in the flow, from Active Module to Assembly, the link is broken
somewhere.
Do I send the bit-streams in the three Active Module to do reconfiguration,
or the three bit-streams from the assembly?
Besides that, how do I find information regarding the AREA constraints? My
chip is Vertex-2Pro 8000K. I need to see
find out the X##Y## are defined in the respective documents and how to use
it.
What is the probability of burning a chip when the synthesis, say, is no
good and caused contention...or any sorts of messed-up
errors in the bit-stream?
Best Regards,
Kelvin.
set XIL_MAP_MULTI_IN_PORTS=1
@echo Running Initial Stage (Top)
@echo =====================
cd Top\Initial
copy ..\..\Src\calctop.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..
@echo Running Initial Stage (Top1)
@echo =====================
cd Top1\Initial
copy ..\..\Src\calctop1.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..
@echo Running Initial Stage (Top2)
@echo =====================
cd Top2\Initial
copy ..\..\Src\calctop2.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..
@echo Running Active module (pushbutton)
@echo =====================
cd Modules\pushbutton
copy ..\..\Src\pushbutton.edf pushbutton.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (lcd_driver)
@echo =====================
cd ..\lcd_driver
copy ..\..\Src\lcd_driver.edf lcd_driver.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (capture)
@echo =====================
cd ..\capture
copy ..\..\Src\capture.edf capture.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (adder)
@echo =====================
cd ..\adder
copy ..\..\Src\adder.edf adder.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (subtractor)
@echo =====================
cd ..\subtractor
copy ..\..\Src\subtractor.edf subtractor.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Assemble Stage (Top)
@echo ======================
cd ..\..\Top\Assemble
copy ..\..\Src\calctop.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
@echo Running Assemble Stage (Top1)
@echo ======================
cd ..\..\Top1\Assemble
copy ..\..\Src\calctop1.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
@echo Running Assemble Stage (Top2)
@echo ======================
cd ..\..\Top2\Assemble
copy ..\..\Src\calctop2.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
cd ..\..
ONE
I am reading the sample design in XAPP290, regarding the partial
reconfiguration of Vertex class FPGAs.
I want to know what is the purpose of the Assembly, it seems to me, after
assembly, all three bit streams
are same 42Kb, meaning the full length.
I feel that, in the flow, from Active Module to Assembly, the link is broken
somewhere.
Do I send the bit-streams in the three Active Module to do reconfiguration,
or the three bit-streams from the assembly?
Besides that, how do I find information regarding the AREA constraints? My
chip is Vertex-2Pro 8000K. I need to see
find out the X##Y## are defined in the respective documents and how to use
it.
What is the probability of burning a chip when the synthesis, say, is no
good and caused contention...or any sorts of messed-up
errors in the bit-stream?
Best Regards,
Kelvin.
set XIL_MAP_MULTI_IN_PORTS=1
@echo Running Initial Stage (Top)
@echo =====================
cd Top\Initial
copy ..\..\Src\calctop.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..
@echo Running Initial Stage (Top1)
@echo =====================
cd Top1\Initial
copy ..\..\Src\calctop1.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..
@echo Running Initial Stage (Top2)
@echo =====================
cd Top2\Initial
copy ..\..\Src\calctop2.edf calctop.edf
call initial.cmd
if errorlevel 1 goto DONE
cd ..\..
@echo Running Active module (pushbutton)
@echo =====================
cd Modules\pushbutton
copy ..\..\Src\pushbutton.edf pushbutton.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (lcd_driver)
@echo =====================
cd ..\lcd_driver
copy ..\..\Src\lcd_driver.edf lcd_driver.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (capture)
@echo =====================
cd ..\capture
copy ..\..\Src\capture.edf capture.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (adder)
@echo =====================
cd ..\adder
copy ..\..\Src\adder.edf adder.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Active module (subtractor)
@echo =====================
cd ..\subtractor
copy ..\..\Src\subtractor.edf subtractor.edf
call active.cmd
if errorlevel 1 goto DONE
@echo Running Assemble Stage (Top)
@echo ======================
cd ..\..\Top\Assemble
copy ..\..\Src\calctop.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
@echo Running Assemble Stage (Top1)
@echo ======================
cd ..\..\Top1\Assemble
copy ..\..\Src\calctop1.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
@echo Running Assemble Stage (Top2)
@echo ======================
cd ..\..\Top2\Assemble
copy ..\..\Src\calctop2.edf calctop.edf
call assemble.cmd
if errorlevel 1 goto DONE
cd ..\..