question regarding SV always_ff and 'blocking timing control

[Suman]

Hello Experts,
In IEEE 1800-2005 LRM (Sec 11.3), it says :
"The always_ff block imposes the restriction that it contains one and
only one event control and no blocking timing controls".
My question is, what is "blocking timing control" ? The LRM does not
say anything about it.

Should the following piece get synthesized ?
----------
always_ff @(posedge clock iff reset == 1 or negedge reset)
if (!reset)
#1 current_state <= S0; // <------ Is there any blocking timing
control ?
else
current_state <= next_state;
------------

Thanks in advance,
Suman.

 

[Jonathan Bromley]

On 15 Jun 2006 06:54:39 -0700, "Suman" <suman.nandan@gmail.com> wrote:

Hello Experts,
In IEEE 1800-2005 LRM (Sec 11.3), it says :
"The always_ff block imposes the restriction that it contains one and
only one event control and no blocking timing controls".
My question is, what is "blocking timing control" ? The LRM does not
say anything about it.

Should the following piece get synthesized ?
----------
always_ff @(posedge clock iff reset == 1 or negedge reset)
if (!reset)
#1 current_state <= S0; // <------ Is there any blocking timing

Yes, that's exactly the sort of thing that always_ff prohibits.
The obvious point is that if you put the process to sleep for
any non-zero length of time, it might miss the next (posedge clock).

Nonblocking timing controls such as

current_state <= #1 S0;

are acceptable.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[dipesh.trivedi]

hello friends,
i am a new verilog user.
i have used the VHDL as a design lang. but in VHDL the time specified
constructs wasnt synthesible. they are ignore at the time of synthesis.
so i think it wont be synthesisible wid time construct. it will ignore
it.

if am wrong then pls correct me.
am new to the Vlog lang. and am doin verification using it. so know
less about the design use of it.



Jonathan Bromley wrote:

On 15 Jun 2006 06:54:39 -0700, "Suman" <suman.nandan@gmail.com> wrote:

Hello Experts,
In IEEE 1800-2005 LRM (Sec 11.3), it says :
"The always_ff block imposes the restriction that it contains one and
only one event control and no blocking timing controls".
My question is, what is "blocking timing control" ? The LRM does not
say anything about it.

Should the following piece get synthesized ?
----------
always_ff @(posedge clock iff reset == 1 or negedge reset)
if (!reset)
#1 current_state <= S0; // <------ Is there any blocking timing

Yes, that's exactly the sort of thing that always_ff prohibits.
The obvious point is that if you put the process to sleep for
any non-zero length of time, it might miss the next (posedge clock).

Nonblocking timing controls such as

current_state <= #1 S0;

are acceptable.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.