Question regarding borrow out bit in a subtractor

R

Rishi Dhupar

Guest
Hi,

Trying to implement an ALU, everything but the subtractor is working.
I cannot get the borrow out of the subtractor to work. I believe I did
it correctly. Here is my entity and a little sniplet of code for the
subtractor.

Thanks for the help.
RishiD

entity hw3 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
S : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
Flag : out std_logic);
end hw3;

architecture Behavioral of hw3 is
signal TempF : std_logic_vector(4 downto 0);
signal twoCompB : std_logic_vector(3 downto 0);
begin
twoCompB <= not (B) + 1;
....
TempF <= ('0' & A) + (twoCompB(3) & twoCompB);
....
F <= TempF(3 downto 0);
Flag <= TempF(4);
end Behavioral;
 
Rishi Dhupar wrote:
Hi,

Trying to implement an ALU, everything but the subtractor is working.
I cannot get the borrow out of the subtractor to work. I believe I did
it correctly. Here is my entity and a little sniplet of code for the
subtractor.

Thanks for the help.
RishiD

entity hw3 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
S : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
Flag : out std_logic);
end hw3;

architecture Behavioral of hw3 is
signal TempF : std_logic_vector(4 downto 0);
signal twoCompB : std_logic_vector(3 downto 0);
begin
twoCompB <= not (B) + 1;
...
TempF <= ('0' & A) + (twoCompB(3) & twoCompB);
...
F <= TempF(3 downto 0);
Flag <= TempF(4);
end Behavioral;
Click to expand...
Are your vectors signed or unsigned? You appended a zero to the A
vector MSb. Should you be sign extending like you did on the B input?
 
Not sure exactly how to even sign extend a vector. So I am guessing
they are unsigned.
rickman wrote:
Rishi Dhupar wrote:
Hi,

Trying to implement an ALU, everything but the subtractor is working.
I cannot get the borrow out of the subtractor to work. I believe I did
it correctly. Here is my entity and a little sniplet of code for the
subtractor.

Thanks for the help.
RishiD

entity hw3 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
S : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
Flag : out std_logic);
end hw3;

architecture Behavioral of hw3 is
signal TempF : std_logic_vector(4 downto 0);
signal twoCompB : std_logic_vector(3 downto 0);
begin
twoCompB <= not (B) + 1;
...
TempF <= ('0' & A) + (twoCompB(3) & twoCompB);
...
F <= TempF(3 downto 0);
Flag <= TempF(4);
end Behavioral;

Are your vectors signed or unsigned? You appended a zero to the A
vector MSb. Should you be sign extending like you did on the B input?
Click to expand...
 
Not sure exactly how to even sign extend a vector. So I am guessing
they are unsigned.
Click to expand...
As far as I am aware '+' is not defined for std_logic_vector so I'm
guessing you are not using the standard ieee library. Use the
following.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

(Search the newsgroup for the reasons why).

Searching with "signed unsigned bromley" seems to get some good stuff.
 
At this point I think it is pretty clear that this is a homework
assignment. I expect you may not have written the code shown below.
You say you don't know how to sign extend a vector and that is already
being done in the code!

(twoCompB(3) & twoCompB)

If you don't understand something about the assignment, you can ask
specific questions and I am sure you will get help. But no one here
wants to do your homework for you. Lord knows I would love to have
people doing my work for me!!! There is a dock on a lake that needs my
urgent attention and all this work gets in the way... ;^)


Rishi Dhupar wrote:
Not sure exactly how to even sign extend a vector. So I am guessing
they are unsigned.
rickman wrote:
Rishi Dhupar wrote:
Hi,

Trying to implement an ALU, everything but the subtractor is working.
I cannot get the borrow out of the subtractor to work. I believe I did
it correctly. Here is my entity and a little sniplet of code for the
subtractor.

Thanks for the help.
RishiD

entity hw3 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
S : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
Flag : out std_logic);
end hw3;

architecture Behavioral of hw3 is
signal TempF : std_logic_vector(4 downto 0);
signal twoCompB : std_logic_vector(3 downto 0);
begin
twoCompB <= not (B) + 1;
...
TempF <= ('0' & A) + (twoCompB(3) & twoCompB);
...
F <= TempF(3 downto 0);
Flag <= TempF(4);
end Behavioral;

Are your vectors signed or unsigned? You appended a zero to the A
vector MSb. Should you be sign extending like you did on the B input?
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top