Question regarding bitstream generation

[Richi]

Hi all,

I have a very simple VHDL module, consisting of a few lines of code.
The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST
adds lots of extra information so that the bitstream
can run standalone on a FPGA.

However, for my purpose it would be interesting to see the size of the
bitstream of the module alone without any extra bits and pieces, just
the vaniall module alone. Is there an option in Xilinx ISE 12.1 that
allows me to do that?

Many thanks,
Richi

 

[maxascent]

I far as I am aware you cant change the bitstream size. I dont really se
why you would want to do that.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

 

[glen herrmannsfeldt]

Richi <richardmolgner2@gmail.com> wrote:

I have a very simple VHDL module, consisting of a few lines of code.
The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST
adds lots of extra information so that the bitstream
can run standalone on a FPGA.

However, for my purpose it would be interesting to see the size of the
bitstream of the module alone without any extra bits and pieces, just
the vaniall module alone. Is there an option in Xilinx ISE 12.1 that
allows me to do that?

If you just want to see how much 'information' is in the file
(in terms of information theory) try compressing it with a program
such as gzip. There will likely be many empty CLBs with the
same bit pattern for each one. A good compress program should find
that pattern and compress it out. That should be pretty close
to what you are asking for. You could, of course, decompress
it in software or hardware on board, just before loading it
into the FPGA. It is more usual to use a large enough ROM, but
there is no rule requiring that.

-- glen

 

[Gabor]

On Monday, February 28, 2011 9:32:26 AM UTC-5, Richi wrote:

Hi all,

I have a very simple VHDL module, consisting of a few lines of code.
The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST
adds lots of extra information so that the bitstream
can run standalone on a FPGA.

However, for my purpose it would be interesting to see the size of the
bitstream of the module alone without any extra bits and pieces, just
the vaniall module alone. Is there an option in Xilinx ISE 12.1 that
allows me to do that?

Many thanks,
Richi

You didn't specify the device family, but most Xilinx
parts support bitstream compression. Their algorithm
is much simpler than you get from gzip or winzip, but
for a mostly empty part the compression should be
significant. You can enable compression in the BitGen
options.

-- Gabor

 

[richi]

You didn't specify the device family, but most Xilinx
parts support bitstream compression. Their algorithm
is much simpler than you get from gzip or winzip, but
for a mostly empty part the compression should be
significant. You can enable compression in the BitGen
options.

Thanks for all the answers of you guys, very helpful. It
is a Xilinx Virtex 5 board. I will try it with the compression
option. Essentially, I have a couple of designs that I wanna
use for partial reconfiguration (so they are part of a bigger
bitstream), and I would like to know their sizes in kB to see how much
memory I have to allocate on SRAM where I can hold then these
bitstreams. Of course I could do the partial bitstream generation but
this is a rather long process so I would prefer to get an estimation of
the size of the bitstream in a faster way. So when using the compression
algorithm this comes pretty close to the actual size of the partial
bitstream?

Thanks in advance,
R.

 

[Thomas Stanka]

On 28 Feb., 15:32, Richi <richardmolgn...@gmail.com> wrote:

I have a very simple VHDL module, consisting of a few lines of code.
The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST
adds lots of extra information so that the bitstream
can run standalone on a FPGA.

Complexity of a design is NOT measured in size of the bitstream. In
first glance each design for same device has similar bitstream size.
If you like to learn something about complexity of a module, you stop
after synthesis or layout and start counting CLBs (or registers,...)

 

[Matthieu Michon]

On Mon, 28 Feb 2011 06:32:26 -0800 (PST)
Richi <richardmolgner2@gmail.com> wrote:

I have a very simple VHDL module, consisting of a few lines of code.
The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST
adds lots of extra information so that the bitstream
can run standalone on a FPGA.

AFAIK, with the default settings, "bitgen" generates bitstreams which are identical in size for a given target device, regardless of the design contents.

You can make the analogy with a bitmap image file : when using the BMP file format, the file size is identical regardless of it contents (high-def very shrap image; plain all white; ...). Using a compressed file type (jpeg, png, ...) will yield different results.

However, for my purpose it would be interesting to see the size of the
bitstream of the module alone without any extra bits and pieces, just
the vaniall module alone. Is there an option in Xilinx ISE 12.1 that
allows me to do that?

Yes. Look for a option called bitstream compression in the bitgen options.


--
Matthieu Michon <prenom.nom@gmail.com>