question on synthesis

[googler]

Given the VHDL code below (an edge-triggered flip flop), isn't the
check (in first if statement) on event attribute redundant? (because,
the sensitivity list already has CLK signal which ensures the process
is entered only when there's an event on CLK).

process(CLK)
begin
if (CLK'event and CLK = '1') then
if (ENA = '1') then
Q <= D;
end if;
end if;
end process;

Pls comment, since this is what I see in most textbooks and examples.

Secondly, are the loops (for, while etc) synthesizable in VHDL? where
can I get a list of all VHDL syntax elements that are synthesizable
(and the ones that are not)?

Thank you.

 

[Reiner Huober]

isn't the
check (in first if statement) on event attribute redundant?

Yes, but compare this (a more common pattern)

process(CLK,RESET)
begin
if (CLK'event and CLK='1') then
...

Now the CLK'event is not redundant any more. You can leave CLK'event in
your case for readability purposes.

--

Statements which can be converted to a truth table can also be
synthesized, like

Shifter:
process(clk=
begin
if clk'event and clk='1' then
for i=1 to v'high loop
v(i-1)<=v(i)
end loop;
end if;
end process;
A synchronous barrel shifter, the shift is done in parallel here.

The synthesizable subset of VHDL depends on the synthesis tool. AFAIK
there is a standard (in progress) which should contain the least common
denominator.

Hubble.

 

[Jonathan Bromley]

On 10 Oct 2005 02:30:48 -0700, "googler" <pinaki_m77@yahoo.com> wrote:

Given the VHDL code below (an edge-triggered flip flop), isn't the
check (in first if statement) on event attribute redundant? (because,
the sensitivity list already has CLK signal which ensures the process
is entered only when there's an event on CLK).

process(CLK)
begin
if (CLK'event and CLK = '1') then

Yes, it's redundant. But supposing you add an asynch
reset to your code....

process (clk, rst)
begin
if (rst = '1') then
...
elsif (clk'event and clk = '1') then
...

Now, if you skip the "clk'event", you will get a spurious
clock action if the clock happens to be high on the falling
edge of rst. Verilog gets around this with its @(posedge clk)
event control construct, but pays for it in other ways

Pls comment, since this is what I see in most textbooks and examples.

Get a new textbook. For about ten years, the more appropriate thing
to do has been

if rising_edge(clk) then
...

Clearer and nicer. However, if you use the traditional form,
synthesis tools generally require the 'event test even though
it's technically redundant in your case.

Secondly, are the loops (for, while etc) synthesizable in VHDL?

'for' is synthesisable if the loop has constant bounds, and
contains no timing constructs.

'while' is probably not synthesisable, although some tools
allow it as an extension.

If you put a clock-wait inside a loop, like this...

for i in 1 to 20 loop
wait until rising_edge(clk);
end loop;

then you have created an implicit state machine; some
tools can synthesise such things, but it's best avoided
unless you are simply exploring the limits of what
synthesis can do. A few years ago there was a fashion
for "behavioural synthesis" tools that could handle such
things, but it never really caught on - too tricky to
use, understand and control.

can I get a list of all VHDL syntax elements that are synthesizable
(and the ones that are not)?

Yes, in the docs for your synthesis tool. You could also take a
look at the VHDL synthesisable subset standard IEEE1076.6.
--
Jonathan Bromley, Consultant

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