question on driving signal in SV

Guest
In my program block, I have a non-blocking statment
top.dut.mul.a <= 1;

It this valure for siganl will be asserted in beginning of the current
timeslot (or in the next time slot.) I am confuse, as this code will be
executed in Reactive region. How this effects active region of the
timeslot? can someone breakdown what SV is doing here.

and can I assert value in next cycle by using blocking statment?
top.dut.mul.a = 1;

thanks.
 
Hi, ankitks,

IMO, from "SystemVerilog Event Regions, Race Avoidance & Guidelines"
P.14 by Clifford Cummings, we know reactive region means re-active NBA
region (re-schedule NBA assignment in program to NBA).

So, the procedure maybe (I guess)
NBA in DUT -> Reactive Region -> NBA in Program. So NBA in Program will
not affect NBA in DUT.

BTW, I heard that we can only refer signals in DUT, but can we modify
signals in DUT? Anyone know that?

Thanks,
Shenli

ankitks@yahoo.com wrote:
In my program block, I have a non-blocking statment
top.dut.mul.a <= 1;

It this valure for siganl will be asserted in beginning of the current
timeslot (or in the next time slot.) I am confuse, as this code will be
executed in Reactive region. How this effects active region of the
timeslot? can someone breakdown what SV is doing here.

and can I assert value in next cycle by using blocking statment?
top.dut.mul.a = 1;

thanks.
Click to expand...
 
Hi,

Add a link describe the event execution order (same as my guess)
http://www.project-veripage.com/program_blocks_3.php

This link said
1. All variables local to a program can only be assigned using blocking
assignment.
2. All other variables must be assigned using non-blocking assignments.


So, top.dut.mul.a = 1; may be not correct.

Thanks,
Davy

Shenli wrote:
Hi, ankitks,

IMO, from "SystemVerilog Event Regions, Race Avoidance & Guidelines"
P.14 by Clifford Cummings, we know reactive region means re-active NBA
region (re-schedule NBA assignment in program to NBA).

So, the procedure maybe (I guess)
NBA in DUT -> Reactive Region -> NBA in Program. So NBA in Program will
not affect NBA in DUT.

BTW, I heard that we can only refer signals in DUT, but can we modify
signals in DUT? Anyone know that?

Thanks,
Shenli

ankitks@yahoo.com wrote:
In my program block, I have a non-blocking statment
top.dut.mul.a <= 1;

It this valure for siganl will be asserted in beginning of the current
timeslot (or in the next time slot.) I am confuse, as this code will be
executed in Reactive region. How this effects active region of the
timeslot? can someone breakdown what SV is doing here.

and can I assert value in next cycle by using blocking statment?
top.dut.mul.a = 1;

thanks.
Click to expand...
 
Hi all,

Non-blocking assignment spawn (NBA) in program is Reactive -> NBA.

But how about the traditional NBA in module (not program) like
"@(posedge clk) DOUT<= #1 DIN;", the simulator will follow what
order to spawn NBA in module with delay to another time slot?

Best regards,
Davy

Shenli wrote:
Hi,

Add a link describe the event execution order (same as my guess)
http://www.project-veripage.com/program_blocks_3.php

This link said
1. All variables local to a program can only be assigned using blocking
assignment.
2. All other variables must be assigned using non-blocking assignments.


So, top.dut.mul.a = 1; may be not correct.

Thanks,
Davy

Shenli wrote:
Hi, ankitks,

IMO, from "SystemVerilog Event Regions, Race Avoidance & Guidelines"
P.14 by Clifford Cummings, we know reactive region means re-active NBA
region (re-schedule NBA assignment in program to NBA).

So, the procedure maybe (I guess)
NBA in DUT -> Reactive Region -> NBA in Program. So NBA in Program will
not affect NBA in DUT.

BTW, I heard that we can only refer signals in DUT, but can we modify
signals in DUT? Anyone know that?

Thanks,
Shenli

ankitks@yahoo.com wrote:
In my program block, I have a non-blocking statment
top.dut.mul.a <= 1;

It this valure for siganl will be asserted in beginning of the current
timeslot (or in the next time slot.) I am confuse, as this code will be
executed in Reactive region. How this effects active region of the
timeslot? can someone breakdown what SV is doing here.

and can I assert value in next cycle by using blocking statment?
top.dut.mul.a = 1;

thanks.
Click to expand...
 
Hi all,

Non-blocking assignment spawn (NBA) in program is Reactive -> NBA.

But how about the traditional NBA in module (not program) like
"@(posedge clk) DOUT<= #1 DIN;", the simulator will follow what
order to spawn NBA in module with delay to another time slot?

Best regards,
Davy

Shenli wrote:
Hi,

Add a link describe the event execution order (same as my guess)
http://www.project-veripage.com/program_blocks_3.php

This link said
1. All variables local to a program can only be assigned using blocking
assignment.
2. All other variables must be assigned using non-blocking assignments.


So, top.dut.mul.a = 1; may be not correct.

Thanks,
Davy

Shenli wrote:
Hi, ankitks,

IMO, from "SystemVerilog Event Regions, Race Avoidance & Guidelines"
P.14 by Clifford Cummings, we know reactive region means re-active NBA
region (re-schedule NBA assignment in program to NBA).

So, the procedure maybe (I guess)
NBA in DUT -> Reactive Region -> NBA in Program. So NBA in Program will
not affect NBA in DUT.

BTW, I heard that we can only refer signals in DUT, but can we modify
signals in DUT? Anyone know that?

Thanks,
Shenli

ankitks@yahoo.com wrote:
In my program block, I have a non-blocking statment
top.dut.mul.a <= 1;

It this valure for siganl will be asserted in beginning of the current
timeslot (or in the next time slot.) I am confuse, as this code will be
executed in Reactive region. How this effects active region of the
timeslot? can someone breakdown what SV is doing here.

and can I assert value in next cycle by using blocking statment?
top.dut.mul.a = 1;

thanks.
Click to expand...
 
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