V
valentin tihomirov
Guest
Below are two architectures (RTL2 and RTL3). They have idendtical behaviour.
Outputs (O1 and O2) are depending on STATE. Which architecure is more
preferrable for FPGA?
Which encoding of states is preferred for FPGAs (onehot, gray, sequential)?
Thanks.
architecture RTL2 of MF is
type STATE_TYPE is
(S0, S1, S2, S3);
signal state: STATE_TYPE;
begin
SEQUENCE : process
begin
-- wait on CLK until CLK = '1';
wait until CLK = '1';
O1 <= '0';
O2 <= '0';
if reset='1' then
STATE <= S0;
else
case STATE is
when S0 =>
O1 <= '0';
O2 <= '0';
STATE <= S1;
when S1 =>
O1 <= '0';
O2 <= '1';
STATE <= S2;
when S2 =>
O1 <= '1';
O2 <= '0';
STATE <= S3;
when S3 =>
O1 <= '1';
O2 <= '1';
STATE <= S0;
end case;
end if;
end process ;
end RTL2;
architecture RTL3 of MF is
type STATE_TYPE is
(S0, S1, S2, S3);
signal state: STATE_TYPE;
begin
COMB: process(STATE)
begin
case STATE is
when S0 =>
O1 <= '0';
O2 <= '0';
when S1 =>
O1 <= '0';
O2 <= '1';
when S2 =>
O1 <= '1';
O2 <= '0';
when S3 =>
O1 <= '1';
O2 <= '1';
end case;
end process;
SEQUENCE : process
begin
wait on CLK until CLK = '1';
-- wait until CLK = '1';
if reset='1' then
STATE <= S0;
else
case STATE is
when S0 =>
STATE <= S1;
when S1 =>
STATE <= S2;
when S2 =>
STATE <= S3;
when S3 =>
STATE <= S0;
end case;
end if;
end process ;
end RTL3;
Outputs (O1 and O2) are depending on STATE. Which architecure is more
preferrable for FPGA?
Which encoding of states is preferred for FPGAs (onehot, gray, sequential)?
Thanks.
architecture RTL2 of MF is
type STATE_TYPE is
(S0, S1, S2, S3);
signal state: STATE_TYPE;
begin
SEQUENCE : process
begin
-- wait on CLK until CLK = '1';
wait until CLK = '1';
O1 <= '0';
O2 <= '0';
if reset='1' then
STATE <= S0;
else
case STATE is
when S0 =>
O1 <= '0';
O2 <= '0';
STATE <= S1;
when S1 =>
O1 <= '0';
O2 <= '1';
STATE <= S2;
when S2 =>
O1 <= '1';
O2 <= '0';
STATE <= S3;
when S3 =>
O1 <= '1';
O2 <= '1';
STATE <= S0;
end case;
end if;
end process ;
end RTL2;
architecture RTL3 of MF is
type STATE_TYPE is
(S0, S1, S2, S3);
signal state: STATE_TYPE;
begin
COMB: process(STATE)
begin
case STATE is
when S0 =>
O1 <= '0';
O2 <= '0';
when S1 =>
O1 <= '0';
O2 <= '1';
when S2 =>
O1 <= '1';
O2 <= '0';
when S3 =>
O1 <= '1';
O2 <= '1';
end case;
end process;
SEQUENCE : process
begin
wait on CLK until CLK = '1';
-- wait until CLK = '1';
if reset='1' then
STATE <= S0;
else
case STATE is
when S0 =>
STATE <= S1;
when S1 =>
STATE <= S2;
when S2 =>
STATE <= S3;
when S3 =>
STATE <= S0;
end case;
end if;
end process ;
end RTL3;