Question for IP configurability design

[Charles.Zhao]

When I design a large configurable IP, which is composed by some large
components, I want the compiler would report warnings or errors if the
IP integrate engineer do a wrong components configuration for this IP.
How can I do that?

for example, if my IP called A, it includes three main component
b,c,d. Each component b,c,d would have a number of instances, but some
of instances number combination is not supported. for example, if you
configure A has 3 b, 2 c, 1 d, that's allowed. But if you configure A
has 3 b, 2 c, 2 d, it's not allowed for 2 d is illegal. And I want it
will report out at the beginning of the code compilation process. Does
verilog or SV have this kind of function in syntax? Or you have some
other method to handle that?

Please give me your opinion.

 

[Jonathan Bromley]

On Mon, 29 Jun 2009 01:19:56 -0700 (PDT), "Charles.Zhao"
<Charles.Zhao1112@gmail.com> wrote:

When I design a large configurable IP, which is composed by some large
components, I want the compiler would report warnings or errors if the
IP integrate engineer do a wrong components configuration for this IP.
How can I do that?

VHDL has always allowed you to do this. You can write a function
that processes your parameters (generics). If that function
is used to determine the value of another constant, it will be
called at elaboration time. The function can include assertions
to check that the parameter values are sensible.

In Verilog it's a little more difficult, but once again you
could rely on the evaluation of a constant function. Sadly
in Verilog-2005 a constant function can't call $display
system tasks (strictly speaking it ignores them) so it's
a little tricky to get an error message out of this.
You might be able to get the constant function to create
a value that would force an elaboration error....

module very_flexible #(parameter mumble = 1) (...);
// mumble must be greater than zero!!!!

// This code is to generate an error if mumble<=0.
// It has no other purpose.
wire [1:0] parameter_checker;
function integer elab_error_check;
input integer p;
if (p<=0)
elab_error_check = 2;
else
elab_error_check = 0;
endfunction
wire [1:0] parameter_out_of_range =
parameter_checker[1:elab_error_check(mumble)];
// bad parameter will give a range error for this
...
endmodule

Finally....

The upcoming revision of SystemVerilog (likely to be published
around the end of this year) includes "elaboration-time
assertions" that allow you to include precisely this kind
of check, with fully configurable diagnostic messages.
--
Jonathan Bromley, Consultant

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