Question for a simulator error

[Charles.Zhao]

hi everyone,
My design is a complex IP written by verilog. Recently, I run
simulation on Questa 6.5b. But a wired situation occured, one of my
sub module's inner signal is always 'x' state from start of
simulation. I think it had been always 'x' state in every simulation
since we began our verification work, because our verification had not
reached this part of logic. Now I noticed this situation. The most
wired is that in source code, it just a normal always block. For an
example,

always @(*)
A = 1'b0;

While in waveform of Questa, It's a x state.
I am totally puzzled by this issue. How can become like this? Bugs for
Questa? Or a verilog gotchas? Hope for somebody's opinion.

Charles

 

[Jonathan Bromley]

On Thu, 2 Jul 2009 04:10:30 -0700 (PDT), "Charles.Zhao"
<Charles.Zhao1112@gmail.com> wrote:

The most wired is that...

Just for future reference: the word you're probably
looking for is "weird" (strange, spooky, inexplicable).

always @(*)
A = 1'b0;

While in waveform of Questa, It's a x state.

And so it should be.

always @* builds a sensitivity list from
anything that is read, but not written,
in the block. Your block does not read
any variables or nets, so there's no
sensitivity list. So the always block
stalls at the event control @() and
never executes your assignment.

I am totally puzzled by this issue. How can become like this? Bugs for
Questa? Or a verilog gotchas?

The latter.

Easiest fix: declare A as a wire, and then do

assign A = 1'b0;
--
Jonathan Bromley, Consultant

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[Muzaffer Kal]

On Thu, 02 Jul 2009 13:20:48 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

Easiest fix: declare A as a wire, and then do

assign A = 1'b0;

Or you can declare and initialize at the same time ie

wire A = 1'b0;

or if it's a register ie:

reg A;

then add
initial A = 0;

-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com