Question about Xilinx packages and CLB ordering

[Lawrence Nospam]

I have been designing using the Virtex-II
family in the FG456/FG676 footprints.

I imagine that there is a nice left-to-right
data flow on-chip which fits nicely onto the
CLBs, which increase in address from the left
to the right as seen from above. Just like
one would expect a schematic of a board of
MSI logic to have.


I want to make a board with a similar layout
(data sources to the left, sinks to the right)
but I need to use a bigger chip.

I have just noticed that the FF896/FF1152
footprints have the die flipped over.

This seems to mean that data on my board will
have to flow "right-to-left" inside the FPGA.
From larger X addresses to smaller ones.


What's the story here?

Two questions:

1) Why didn't Xilinx mirror the masks on their
larger chips (4000, 6000, 8000) so that flip-chip
bonding of the big chip would result in identical
CLB placement, as seen from above, as you get with
the non-flipped smaller chips?

2) If I take a design which flows left-to-right in
a non-flipped package and re-PAR it into a flipped
package, will the performance be impacted? Percentage?

(For instance, I replace an XC2V2000 in FG676 with
an XC2V2000 in FF896, with the same PC board layout
of data-in/data-out but a slightly bigger chip area)

Thanks for the benefit of your experience:

Lawrence NoSpam

 

[Symon]

Lawrence,
To answer 2), the performance won't be impacted by flipping. There are just
as many left to right connections as right to left. And vice versa! Have a
look in the FPGA editor if you like. This answers 1)!
Cheers, Syms.
"Lawrence Nospam" <llbutcher@worldnet.att.net> wrote in message
news:JIzxc.31862$Gx4.18088@bgtnsc04-news.ops.worldnet.att.net...

1) Why didn't Xilinx mirror the masks on their
larger chips (4000, 6000, 8000) so that flip-chip
bonding of the big chip would result in identical
CLB placement, as seen from above, as you get with
the non-flipped smaller chips?

2) If I take a design which flows left-to-right in
a non-flipped package and re-PAR it into a flipped
package, will the performance be impacted? Percentage?