Question about thermometer code

D

Daku

Guest
Could some Verilog guru please help ? I came upon the following code
snippet:
function [6:0] bin2ther;
input [2:0] bin;
begin
case (bin)
3'h0: bin2ther = 7'b0000000;
3'h1: bin2ther = 7'b0000001;
3'h2: bin2ther = 7'b0000011;
3'h3: bin2ther = 7'b0000111;
3'h4: bin2ther = 7'b0001111;
3'h5: bin2ther = 7'b0011111;
3'h6: bin2ther = 7'b0111111;
3'h7: bin2ther = 7'b1111111;
endcase
end
endfunction

What I find confusing is :
Both 'bin' and 'bin2ther' are little-endian, so that
the left-most bit is LSB and rightmost bit MSB - so not the values for
bin2ther be reversed, for example :
3'h1 : bin2ther = 7'b1000000;
Am I confusing something. thanks in advance for your help.
 
On 2011-05-05 11:04:17 +0100, Daku said:

Could some Verilog guru please help ? I came upon the following code
snippet:
function [6:0] bin2ther;
input [2:0] bin;
begin
case (bin)
3'h0: bin2ther = 7'b0000000;
3'h1: bin2ther = 7'b0000001;
3'h2: bin2ther = 7'b0000011;
3'h3: bin2ther = 7'b0000111;
3'h4: bin2ther = 7'b0001111;
3'h5: bin2ther = 7'b0011111;
3'h6: bin2ther = 7'b0111111;
3'h7: bin2ther = 7'b1111111;
endcase
end
endfunction

What I find confusing is :
Both 'bin' and 'bin2ther' are little-endian, so that
the left-most bit is LSB and rightmost bit MSB - so not the values for
bin2ther be reversed, for example :
3'h1 : bin2ther = 7'b1000000;
Am I confusing something. thanks in advance for your help.
Click to expand...
I don't claim to be a Guru, but the code looks correct to me. I don't
think endianess comes into it.

If you put in a value of 3'h3 you get out the value 7'b0000111. You
havn't got an endian issue till you descide how the input vector and
output vector are stored somewhere, or shown on a bank of LEDs etc.

Verilog, values are LSB is the right most digit, but that's the same
even in big endian and little endian CPU resgisters, bit 0 is the least
significant bit. It's how you decide to store the registers in
consecutive byte addresses that determines endiannes.

Chris
 
On 5/5/2011 5:04 AM, Daku wrote:
Could some Verilog guru please help ? I came upon the following code
snippet:
function [6:0] bin2ther;
input [2:0] bin;
begin
case (bin)
3'h0: bin2ther = 7'b0000000;
3'h1: bin2ther = 7'b0000001;
3'h2: bin2ther = 7'b0000011;
3'h3: bin2ther = 7'b0000111;
3'h4: bin2ther = 7'b0001111;
3'h5: bin2ther = 7'b0011111;
3'h6: bin2ther = 7'b0111111;
3'h7: bin2ther = 7'b1111111;
endcase
end
endfunction

What I find confusing is :
Both 'bin' and 'bin2ther' are little-endian, so that
the left-most bit is LSB and rightmost bit MSB - so not the values for
bin2ther be reversed, for example :
3'h1 : bin2ther = 7'b1000000;
Am I confusing something. thanks in advance for your help.
Click to expand...
Best of my knowledge, endian only refers to byte ordering and not bit
ordering. If you decide your least-significant bit is on the left (like
IBM) this is not little endian. Just a weird bit ordering.

If you have a least-significant byte of a multi-word value at a lower
address this is little-endian.

Chris
 
On May 5, 6:04 am, Daku <dakup...@gmail.com> wrote:
Could some Verilog guru please help ? I came upon the following code
snippet:
function [6:0] bin2ther;
input [2:0] bin;
    begin
    case (bin)
        3'h0: bin2ther = 7'b0000000;
        3'h1: bin2ther = 7'b0000001;
        3'h2: bin2ther = 7'b0000011;
        3'h3: bin2ther = 7'b0000111;
        3'h4: bin2ther = 7'b0001111;
        3'h5: bin2ther = 7'b0011111;
        3'h6: bin2ther = 7'b0111111;
        3'h7: bin2ther = 7'b1111111;
    endcase
end
endfunction

What I find confusing is :
Both 'bin' and 'bin2ther' are little-endian, so that
the left-most bit is LSB and rightmost bit MSB - so not the values for
bin2ther be reversed, for example :
3'h1 :  bin2ther = 7'b1000000;
Am I confusing something. thanks in advance for your help.
Click to expand...
No matter how you number bits, the least significant
bit is on the right and the most significant is on the
left. [6:0] could be called "little endian" and [0:6]
"big endian". IBM actually uses consistent big endian
for both bits and bytes. However the MSB is on the left
in both cases, just in the little endian case bit 0
is on the right and therefore LSB and in the big endian
case bit 0 is on the left and therefore the MSB.

Assignments keep the left to right order intact. So
for example:

wire [6:0] foo;
wire [0:6] bar;

assign foo = bar;

This will assign as follows:
foo[0] = bar[6]
foo[1] = bar[5]
.. . .
foo[6] = bar[0]

and in either case

assign foo = 7'b0000001;
assign bar = 7'b0000001;

you have a one in the LSB, just the bit number
of the LSB changes, so for foo bit 0 is one, but
for bar bit 6 is one.

Hope this isn't more confusing than helpful.

-- Gabor
 
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