Question about summation function

[Fess]

Hello! I've using VHDL for like 2 years or even more but just today
wondeĐş how it works. Summation function form any package, std_arit
for example operates on two arguments. But this one return
std_logic_vector as a result. So i have no ideas how it works when yo
are using something like this:

signal result : std_logic_vector (15 downto 0);
signal arg_1: std_logic_vector (15 downto 0);
signal arg_2: std_logic_vector (15 downto 0);
signal arg_3: std_logic_vector (15 downto 0);

result <= signed(arg_1) + signed(arg_2) + signed(arg_3);

Any of used summation returns std_logic_vector but then it needs to us
one more summation but it's
undefined for std_logic vector and signed.

It would be great if someone would clarify. Thanks

P.S. sorry for my English(



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[KJ]

Adding two signed will produce a signed, not std_logic_vector.

Kevin Jennings