D
Daku
Guest
Could some Verilog guru please help ? I am trying to model the
following serial parallel converter. The input is a serial bit stream
synchronized with a high-speed master clock (approx 10 GHz). The input
is stored in a 64 bit array. As soon as 64 bits have arrived, a divide-
by-64 clock (feeding off the master clock) goes high and the 64 bits
are converted to 8 parallel bytes. May I know how exactly the parallel
conversion is supposed to occur ? 'fork - join' constructs are not
permissible as they cannot be realized in hardware.
Any hints, suggestions would be of immense help. Thanks in advance.
following serial parallel converter. The input is a serial bit stream
synchronized with a high-speed master clock (approx 10 GHz). The input
is stored in a 64 bit array. As soon as 64 bits have arrived, a divide-
by-64 clock (feeding off the master clock) goes high and the 64 bits
are converted to 8 parallel bytes. May I know how exactly the parallel
conversion is supposed to occur ? 'fork - join' constructs are not
permissible as they cannot be realized in hardware.
Any hints, suggestions would be of immense help. Thanks in advance.