Question about SDRAM timing parameters!

[Vick]

I had this verilog code for 16-bit SDRAM with the timing parameters
namely the :

tCMS,
tCMH,
tCK,
tHZ,
tOH,
tRCD,
tRRD along with a few timing checks.

I have customized the code to 64-bit but having some problems with the
Timing parameters.I chaged them according to the 64-bit SDRAM spec.
but still facing errors.

Any obvious solutions which mite fix the problem.
Here is the line where I get the error:

if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD))
$display("at time %t ERROR: tRCD violation during Read or Write to
Bank 0", $time);


Thnx

 

[shinningstar]

tCMS--CS#, RAS#, CAS#, WE#, DQM# Setup Time
tCMH--CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCK --Clock Cycle Time
tHZ --Data-out high-impedance time
tOH --Data-out hold time
tRCD--ACTIVE to READ or WRITE delay
tRRD--ACTIVE bank a to ACTIVE bank b command
********************************************
I recommend you to read one datasheet of SDRAM, there're also other timing
parameters about SDRAM.
And I also recommend you to read the datasheet of Micron Technology. The
datasheet from this company is very clear and readable.
You can obtain its datasheet from this URL:
http://www.micron.com