Question about post-PAR simulation

[Antonio]

Hi all,
I've got a little question about post Place&Route simulation
in ISE WebPack 5.2 + ModelSim.
How can I do a post-PAR simulation of a VHDL
submodule (i.e. a part of a bigger design that is not
connected to I/O buffers)???
I tryed to uncheck the "Add I/O buffer" (synthesis), to use
the SAVE constraints and/or to uncheck the "Trim
unconnected signals" (mapping), but I've always got
mapping or simulation errors...

Thanks in advance,
Antonio Di Stefano