P
pallav
Guest
Hi,
I'm writing a small tutorial for functional simulation/testbench in
VHDL. My code is show below. I instantiate the UUT as follows:
UUT: NAND2 port map(a_t => a, b_t => b, y_t => y);
I use GHDL (a free VHDL compiler) to compile by saying "ghdl -a
nand2.vhd". I get the following error message:
nand2.vhd:88:32: no declaration for "a"
nand2.vhd:88:42: no declaration for "b"
nand2.vhd:88:52: no declaration for "y"
However, if I change the above line to
UUT: NAND2 port map(a_t, b_t, y_t);
it compiles fine. Is this a synthesizer issue or has the VHDL standard
changed? Some of the tutorials from the net, seem to do it the above
way.
Although I haven't used VHDL for a long time (occasionally use
verilog), I think the first version is also valid?
--------------------------------------------------------------------------------
--
-- VHDL example of 2-input NAND gate and testbench.
--
-- y = !(a & b);
-- a b | y
-- 0 0 | 1
-- 0 1 | 1
-- 1 0 | 1
-- 1 1 | 0
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Module declaration of NAND2
entity NAND2 is
port(a : in std_logic;
b : in std_logic;
y : out std_logic);
end NAND2;
-- We provide two defintions. Note that they are equivalent as far as
the
-- operation of the gate is concerned. Note that no timing (delay)
-- information is present. Thus, this is purely functional.
-- First definition of NAND2
architecture behv1 of NAND2 is
begin
-- x/y to the truth table
process(a, b)
begin
if (a='1' and b='1') then
y <= '0';
else
y <= '1';
end if;
end process;
end behv1;
-- Second defintion of NAND2
architecture behv2 of NAND2 is
begin
y <= a nand b;
end behv2;
--------------------------------------------------------------------------------
-- To make sure that our NAND2 gate is functionally correct, we must
-- write a simple testbench where we instatiate the gate and supply
an
-- exhaustive list of test vectors. The vectors are applied one-by-
one
-- and the output is compared with the expected output.
-- The code below is our testbench to test the NAND2 gate.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- a testbench has no ports!!
entity TEST_NAND2 is
end TEST_NAND2;
architecture TESTBENCH of TEST_NAND2 is
-- component declaration of unit under test (UUT)
component NAND2
port(a : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
-- UUT inputs
signal a_t, b_t : std_logic;
-- UUT outputs
signal y_t : std_logic;
-- exhaustive test vectors (the truth table)
type test_array is array(integer range<>
of std_logic_vector(0 to
2);
constant test_vector : test_array(0 to 3) :=
(('0','0','1'),
('0','1','1'),
('1','0','1'),
('1','1','0'));
-- pick the architecture to simulate. in this case 'behv2'
for UUT: NAND2 use entity work.NAND2(behv2);
begin
-- instantiate UUT and connect the signals (always provide explicit
bindings)
UUT: NAND2 port map(a_t => a, b_t => b, y_t => y);
tb : process
constant PERIOD: time:=10 ns;
variable testv : std_logic_vector(0 to 2);
begin
-- apply one test vector at a time and compare the outputs
for index in test_vector'range loop
testv := test_vector(index);
a_t <= testv(0);
b_t <= testv(1);
wait for PERIOD; -- wait for output to be updated (for timing
simulation)
assert(y_t = testv(2)) -- if output mismatch, report failure
report "Test output mismatch. Faliure." severity error;
end loop;
wait; -- will wait forever
end process tb;
end TESTBENCH;
--------------------------------------------------------------------------------
I'm writing a small tutorial for functional simulation/testbench in
VHDL. My code is show below. I instantiate the UUT as follows:
UUT: NAND2 port map(a_t => a, b_t => b, y_t => y);
I use GHDL (a free VHDL compiler) to compile by saying "ghdl -a
nand2.vhd". I get the following error message:
nand2.vhd:88:32: no declaration for "a"
nand2.vhd:88:42: no declaration for "b"
nand2.vhd:88:52: no declaration for "y"
However, if I change the above line to
UUT: NAND2 port map(a_t, b_t, y_t);
it compiles fine. Is this a synthesizer issue or has the VHDL standard
changed? Some of the tutorials from the net, seem to do it the above
way.
Although I haven't used VHDL for a long time (occasionally use
verilog), I think the first version is also valid?
--------------------------------------------------------------------------------
--
-- VHDL example of 2-input NAND gate and testbench.
--
-- y = !(a & b);
-- a b | y
-- 0 0 | 1
-- 0 1 | 1
-- 1 0 | 1
-- 1 1 | 0
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Module declaration of NAND2
entity NAND2 is
port(a : in std_logic;
b : in std_logic;
y : out std_logic);
end NAND2;
-- We provide two defintions. Note that they are equivalent as far as
the
-- operation of the gate is concerned. Note that no timing (delay)
-- information is present. Thus, this is purely functional.
-- First definition of NAND2
architecture behv1 of NAND2 is
begin
-- x/y to the truth table
process(a, b)
begin
if (a='1' and b='1') then
y <= '0';
else
y <= '1';
end if;
end process;
end behv1;
-- Second defintion of NAND2
architecture behv2 of NAND2 is
begin
y <= a nand b;
end behv2;
--------------------------------------------------------------------------------
-- To make sure that our NAND2 gate is functionally correct, we must
-- write a simple testbench where we instatiate the gate and supply
an
-- exhaustive list of test vectors. The vectors are applied one-by-
one
-- and the output is compared with the expected output.
-- The code below is our testbench to test the NAND2 gate.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- a testbench has no ports!!
entity TEST_NAND2 is
end TEST_NAND2;
architecture TESTBENCH of TEST_NAND2 is
-- component declaration of unit under test (UUT)
component NAND2
port(a : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
-- UUT inputs
signal a_t, b_t : std_logic;
-- UUT outputs
signal y_t : std_logic;
-- exhaustive test vectors (the truth table)
type test_array is array(integer range<>
of std_logic_vector(0 to2);
constant test_vector : test_array(0 to 3) :=
(('0','0','1'),
('0','1','1'),
('1','0','1'),
('1','1','0'));
-- pick the architecture to simulate. in this case 'behv2'
for UUT: NAND2 use entity work.NAND2(behv2);
begin
-- instantiate UUT and connect the signals (always provide explicit
bindings)
UUT: NAND2 port map(a_t => a, b_t => b, y_t => y);
tb : process
constant PERIOD: time:=10 ns;
variable testv : std_logic_vector(0 to 2);
begin
-- apply one test vector at a time and compare the outputs
for index in test_vector'range loop
testv := test_vector(index);
a_t <= testv(0);
b_t <= testv(1);
wait for PERIOD; -- wait for output to be updated (for timing
simulation)
assert(y_t = testv(2)) -- if output mismatch, report failure
report "Test output mismatch. Faliure." severity error;
end loop;
wait; -- will wait forever
end process tb;
end TESTBENCH;
--------------------------------------------------------------------------------