Question about module port names

[Mike]

Hello,


module m0(.port0(in0), .port1(in1[3:0]), .port2({in2a, in2b}));
input [7:0] in0, in1, in2a, in2b;
endmodule

module m1( in0 , in1[3:0] , {in2a, in2b} );
input [7:0] in0, in1, in2a, in2b;
endmodule


I have a question about module port names. I understand the
case where the port is explicitly named (as in all ports of
module m0) and I understand the case where the port is not
explicitly named, but the port expression is simply a
reference (as in the 0th port of module m1). I am not clear
about the other ports of module m1.

clearly, for module m0 the ports are:
0th port: portname="port0", width=8
1st port: portname="port1", width=4
2nd port: portname="port2", width=16

what about module m1?
0th port: portname="in0", width=8
1st port: does portname="in1" but width is only 4?
2nd port: does it even have a portname? width is 16

Thanks in advance,
Mike

 

[ABC]

Hi Mike,

what about module m1?
0th port: portname="in0", width=8
Yes
1st port: does portname="in1" but width is only 4?
Yes
2nd port: does it even have a portname? width is 16
No port name although the tools might auto assign port name but the

connection must be implicit style. Bit width is 16.
I assume you will also have in1[7:4] declared.

Merry X'mas.

Best regards,
ABC

Mike wrote:

Hello,


module m0(.port0(in0), .port1(in1[3:0]), .port2({in2a, in2b}));
input [7:0] in0, in1, in2a, in2b;
endmodule

module m1( in0 , in1[3:0] , {in2a, in2b} );
input [7:0] in0, in1, in2a, in2b;
endmodule


I have a question about module port names. I understand the
case where the port is explicitly named (as in all ports of
module m0) and I understand the case where the port is not
explicitly named, but the port expression is simply a
reference (as in the 0th port of module m1). I am not clear
about the other ports of module m1.

clearly, for module m0 the ports are:
0th port: portname="port0", width=8
1st port: portname="port1", width=4
2nd port: portname="port2", width=16

what about module m1?
0th port: portname="in0", width=8
1st port: does portname="in1" but width is only 4?
2nd port: does it even have a portname? width is 16

Thanks in advance,
Mike

 

[Rob Dekker]

"ABC" <bcang78@gmail.com> wrote in message news:1166976652.673185.62380@h40g2000cwb.googlegroups.com...

Hi Mike,
what about module m1?
0th port: portname="in0", width=8
Yes
1st port: does portname="in1" but width is only 4?
Yes
2nd port: does it even have a portname? width is 16
No port name although the tools might auto assign port name but the
connection must be implicit style. Bit width is 16.
I assume you will also have in1[7:4] declared.

Merry X'mas.

Best regards,
ABC

Just one comment on the bizarre Verilog rules :

module M1 (a) ;
input a ;
endmodule

has one port called a.

module M2 (a,a) ;
input a ;
endmodule

is legal Verilog ('95)
Two ports, but now neither of them has a name...
Qute huh...

Mike wrote:
Hello,


module m0(.port0(in0), .port1(in1[3:0]), .port2({in2a, in2b}));
input [7:0] in0, in1, in2a, in2b;
endmodule

module m1( in0 , in1[3:0] , {in2a, in2b} );
input [7:0] in0, in1, in2a, in2b;
endmodule


I have a question about module port names. I understand the
case where the port is explicitly named (as in all ports of
module m0) and I understand the case where the port is not
explicitly named, but the port expression is simply a
reference (as in the 0th port of module m1). I am not clear
about the other ports of module m1.

clearly, for module m0 the ports are:
0th port: portname="port0", width=8
1st port: portname="port1", width=4
2nd port: portname="port2", width=16

what about module m1?
0th port: portname="in0", width=8
1st port: does portname="in1" but width is only 4?
2nd port: does it even have a portname? width is 16

Thanks in advance,
Mike