Question about including VHDL package

A

ALuPin

Guest
Hi,

I want to include a VHDL package
(http://members.aol.com/vhdlcohen/vhdl/vhdlcode/lfsrstd.vhd)

in my VHDL-testbench. The function lfsr is a random generator (linear
feedback shift register).

But when trying to compile my testbench I get the following error
message:

ERROR : ...tb_serial_parallel_conv_fs.vhd(106): No feasible entries
for subprogram lfsr



What is the problem ? I would appreciate any helpful hint.

(First I compile "image_pb.vhd", then "lfsrstd.vhd" and then my
testbench)

Here is the testbench code:


----------------------------------------
----------------------------------------
library ieee;
library work;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use work.LfsrStd_Pkg.all;

entity tb_serial_parallel_conv_fs is
end tb_serial_parallel_conv_fs;

architecture testbench of tb_serial_parallel_conv_fs is

component serial_parallel_conv_fs
port ( Reset : in std_logic;
Clk_in : in std_logic;
Clk_out : in std_logic;
Fs_data_ser_in : in std_logic;
Valid_in : in std_logic;
Fs_data_par_out : out std_logic_vector(15 downto 0);
Valid_out : out std_logic
);
end component;

signal t_Reset : std_logic;
signal t_Clk_in : std_logic;
signal t_Clk_out : std_logic;
signal t_Fs_data_ser_in : std_logic;
signal t_Valid_in : std_logic;
signal t_Fs_data_par_out : std_logic_vector(15 downto 0);
signal t_Valid_out : std_logic;

begin

u1 : serial_parallel_conv_fs
port map ( Reset => t_Reset,
Clk_in => t_Clk_in,
Clk_out => t_Clk_out,
Fs_data_ser_in => t_Fs_data_ser_in,
Valid_in => t_Valid_in,
Fs_data_par_out => t_Fs_data_par_out,
Valid_out => t_Valid_out
);
---------------------------------------------------------------------
---------------------------------------------------------------------
process
begin
t_Reset <= '1', '0' after 13 ns;
wait;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
process
begin
t_Clk_in <= '1'; wait for 40 ns;
t_Clk_in <= '0'; wait for 40 ns;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
process
begin
t_Clk_out <= '1'; wait for 5 ns;
t_Clk_out <= '0'; wait for 5 ns;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
process(t_Reset, t_Clk_in)
begin
if t_Reset='1' then
t_Fs_data_ser_in <= '0';
t_Valid_in <= '0';

elsif rising_edge(t_Clk_in) then
t_Fs_data_ser_in <= t_Fs_data_ser_in;
t_Valid_in <= '1';

t_Fs_data_ser_in <= LFSR('1'); --???????

end if;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------



end testbench;
 
Declarations for LFSR:
function LFSR(S : Std_Logic_Vector) return Std_Logic_Vector;
function LFSR(S : Std_uLogic_Vector) return Std_uLogic_Vector;

Your call uses it as std_logic/std_ulogic:
t_Fs_data_ser_in <= LFSR('1'); --???????
Click to expand...
If a single bit is appropriate, you still need to make it std_logic_vector:
LFSR("1")

The signal t_Fs_data_ser_in will need to be std_(u)logic_vector.
signal t_Fs_data_ser_in : std_logic_vector(0 downto 0) ;

and then use it in a std_logic context:
t_Fs_Data_ser_in(0)

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ALuPin wrote:
Hi,

I want to include a VHDL package
(http://members.aol.com/vhdlcohen/vhdl/vhdlcode/lfsrstd.vhd)

in my VHDL-testbench. The function lfsr is a random generator (linear
feedback shift register).

But when trying to compile my testbench I get the following error
message:

ERROR : ...tb_serial_parallel_conv_fs.vhd(106): No feasible entries
for subprogram lfsr



What is the problem ? I would appreciate any helpful hint.

(First I compile "image_pb.vhd", then "lfsrstd.vhd" and then my
testbench)

Here is the testbench code:


a> ----------------------------------------
----------------------------------------
library ieee;
library work;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use work.LfsrStd_Pkg.all;

entity tb_serial_parallel_conv_fs is
end tb_serial_parallel_conv_fs;

architecture testbench of tb_serial_parallel_conv_fs is

component serial_parallel_conv_fs
port ( Reset : in std_logic;
Clk_in : in std_logic;
Clk_out : in std_logic;
Fs_data_ser_in : in std_logic;
Valid_in : in std_logic;
Fs_data_par_out : out std_logic_vector(15 downto 0);
Valid_out : out std_logic
);
end component;

signal t_Reset : std_logic;
signal t_Clk_in : std_logic;
signal t_Clk_out : std_logic;
signal t_Fs_data_ser_in : std_logic;
signal t_Valid_in : std_logic;
signal t_Fs_data_par_out : std_logic_vector(15 downto 0);
signal t_Valid_out : std_logic;

begin

u1 : serial_parallel_conv_fs
port map ( Reset => t_Reset,
Clk_in => t_Clk_in,
Clk_out => t_Clk_out,
Fs_data_ser_in => t_Fs_data_ser_in,
Valid_in => t_Valid_in,
Fs_data_par_out => t_Fs_data_par_out,
Valid_out => t_Valid_out
);
---------------------------------------------------------------------
---------------------------------------------------------------------
process
begin
t_Reset <= '1', '0' after 13 ns;
wait;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
process
begin
t_Clk_in <= '1'; wait for 40 ns;
t_Clk_in <= '0'; wait for 40 ns;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
process
begin
t_Clk_out <= '1'; wait for 5 ns;
t_Clk_out <= '0'; wait for 5 ns;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
process(t_Reset, t_Clk_in)
begin
if t_Reset='1' then
t_Fs_data_ser_in <= '0';
t_Valid_in <= '0';

elsif rising_edge(t_Clk_in) then
t_Fs_data_ser_in <= t_Fs_data_ser_in;
t_Valid_in <= '1';

t_Fs_data_ser_in <= LFSR('1'); --???????

end if;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------



end testbench;
Click to expand...
 
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