question about ? : etc

Guest
Hi,

I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code:

assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 :
(cur_count == 2 && clk_enable == 1'b1)? 1 :
(cur_count == 4 && clk_enable == 1'b1)? 1 :
(cur_count == 7 && clk_enable == 1'b1)? 1 :
(cur_count == 10 && clk_enable == 1'b1)? 1 :
(cur_count == 13 && clk_enable == 1'b1)? 1 :
(cur_count == 16 && clk_enable == 1'b1)? 1 :
(cur_count == 18 && clk_enable == 1'b1)? 1 :
(cur_count == 20 && clk_enable == 1'b1)? 1 :
(cur_count == 22 && clk_enable == 1'b1)? 1 :
(cur_count == 24 && clk_enable == 1'b1)? 1 :
(cur_count == 26 && clk_enable == 1'b1)? 1 :
(cur_count == 29 && clk_enable == 1'b1)? 1 :
(cur_count == 32 && clk_enable == 1'b1)? 1 :
(cur_count == 34 && clk_enable == 1'b1)? 1 :
(cur_count == 36 && clk_enable == 1'b1)? 1 :
(cur_count == 38 && clk_enable == 1'b1)? 1 :
(cur_count == 40 && clk_enable == 1'b1)? 1 :
(cur_count == 42 && clk_enable == 1'b1)? 1 :
(cur_count == 45 && clk_enable == 1'b1)? 1 :
(cur_count == 48 && clk_enable == 1'b1)? 1 :
(cur_count == 50 && clk_enable == 1'b1)? 1 :
(cur_count == 52 && clk_enable == 1'b1)? 1 :
(cur_count == 54 && clk_enable == 1'b1)? 1 :
(cur_count == 56 && clk_enable == 1'b1)? 1 :
(cur_count == 58 && clk_enable == 1'b1)? 1 :
(cur_count == 61 && clk_enable == 1'b1)? 1 : 0;

Could you explain it to me?
Thanks.
 
On Saturday, November 17, 2012 7:57:55 PM UTC-5, rxj...@gmail.com wrote:
Hi,



I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the following code:



assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 :

(cur_count == 2 && clk_enable == 1'b1)? 1 :

(cur_count == 4 && clk_enable == 1'b1)? 1 :

(cur_count == 7 && clk_enable == 1'b1)? 1 :

(cur_count == 10 && clk_enable == 1'b1)? 1 :

(cur_count == 13 && clk_enable == 1'b1)? 1 :

(cur_count == 16 && clk_enable == 1'b1)? 1 :

(cur_count == 18 && clk_enable == 1'b1)? 1 :

(cur_count == 20 && clk_enable == 1'b1)? 1 :

(cur_count == 22 && clk_enable == 1'b1)? 1 :

(cur_count == 24 && clk_enable == 1'b1)? 1 :

(cur_count == 26 && clk_enable == 1'b1)? 1 :

(cur_count == 29 && clk_enable == 1'b1)? 1 :

(cur_count == 32 && clk_enable == 1'b1)? 1 :

(cur_count == 34 && clk_enable == 1'b1)? 1 :

(cur_count == 36 && clk_enable == 1'b1)? 1 :

(cur_count == 38 && clk_enable == 1'b1)? 1 :

(cur_count == 40 && clk_enable == 1'b1)? 1 :

(cur_count == 42 && clk_enable == 1'b1)? 1 :

(cur_count == 45 && clk_enable == 1'b1)? 1 :

(cur_count == 48 && clk_enable == 1'b1)? 1 :

(cur_count == 50 && clk_enable == 1'b1)? 1 :

(cur_count == 52 && clk_enable == 1'b1)? 1 :

(cur_count == 54 && clk_enable == 1'b1)? 1 :

(cur_count == 56 && clk_enable == 1'b1)? 1 :

(cur_count == 58 && clk_enable == 1'b1)? 1 :

(cur_count == 61 && clk_enable == 1'b1)? 1 : 0;



Could you explain it to me?

Thanks.
This is similar to C programming language with statement likes:
A=(conditional expression) ? 0x01 : 0x02
your verilog code is a big nested if then else statement.
Hope this help
 
Hi!

assign ce_hciccomp_decode = (cur_count == 0 && clk_enable == 1'b1)? 1 :
(cur_count == 2 && clk_enable == 1'b1)? 1 :
....
Could you explain it to me?
VHDL:
ce_hciccomp_decode <= 1 when (cur_count = 0 AND clk_enable = '1') else
1 when (cur_count = 2 AND clk_enable = '1') else
....

Ralf
 

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