Question about driver, variable?

[fl]

Hi,

On VHDL books, it says that each signal having an assignment has a driver. I
have a question about variable. Has a variable a driver?
Please clarify the concept for me.


Thanks,

 

[Andy]

No, variables do not have a sense of time or scheduled updates, so they do not have "drivers" like signals do.

Note that unless the variable is shared, only one process can update and read it anyway.

The variable contents are updated immediately upon execution of an assignment statement for that variable. The value persists as long as the variable persists (which, in a process, is for the duration of the simulation), until it is updated by a subsequently executed assignment.

The persistence of a variable's values, in synthesis, can imply either a wire or storage (latch or register), depending on the context of updates and accesses to the value.

Andy

 

[Martin Thompson]

fl <rxjwg98@gmail.com> writes:

Hi,

On VHDL books, it says that each signal having an assignment has a driver. I
have a question about variable. Has a variable a driver?
Please clarify the concept for me.

No, a variable does not have a driver.

Variables can only be changed within a process (unlike signals which can
be changed - driven - from multiple processes) and the order in which
assignment happen within that process define what the value of a
variable is at any particular instant during the flow of execution.

HTH,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware